Thermal Characterization of Conductive Filaments in Unipolar Resistive Memories

Abstract

A methodology to estimate the device temperature in resistive random access memories (RRAMs) is presented. Unipolar devices, which are known to be highly influenced by thermal effects in their resistive switching operation, are employed to develop the technique. A 3D RRAM simulator is used to fit experimental data and obtain the maximum and average temperatures of the conductive filaments (CFs) that are responsible for the switching behavior. It is found that the experimental CFs temperature corresponds to the maximum simulated temperatures obtained at the narrowest sections of the CFs. These temperature values can be used to improve compact models for circuit simulation purposes.

1. Introduction

Resistive memories, also known as resistive random access memories (RRAMs), are attracting interest from the scientific community and the industry in the last twelve years as a consequence of their great potential for a wide variety of applications of interest in the electronics landscape [1]. RRAMs can be used as non-volatile memories [2]; several companies commercially use these devices (TSMC for its 40 nm [3], 28 nm [4], and 22 nm [5] nodes; INTEL for its 22 nm [6] node). Another great field of development is linked to neuromorphic engineering [2,7,8,9,10,11,12,13,14,15,16]. In addition, these emerging devices are interesting for hardware cryptography in the context of the Internet of Things ecosystem [17,18,19,20]. Moreover, these devices, and other memristive devices [21], can be employed as radio-frequency switches for mobile communications [1].

RRAM operation is based on resistive switching (RS), whose origin is related to ion movement and concurrent redox reactions inside the dielectric and at the dielectric/electrode interfaces [22,23]. These devices present an outstanding endurance (above >10¹⁰ cycles [24]); they have demonstrated a good speed (<10 ns) and a large resistance window [1]. Their fabrication is compatible with CMOS technology and the devices can be built in compact crossbar structures [2]. RRAMs can be operated with very low power consumption. Resistive memories can be employed in a digital context, where they show two stable resistive states: the high resistance state (HRS) and the low resistance state (LRS); moreover, an analog perspective is appropriate for neuromorphic computing applications [1,7], although their usually exhibited non-linear response could make the weight update more difficult [25]. However, even devices that exhibit abrupt (digital) switching between the HRS and LRS can still be used for the implementation of binarized neural networks [26] or binary weight spike-time-dependent plasticity (STDP) learning rules [27].

The device operation depends on the dielectric and electrode materials. Different types of RRAMs are distinguished depending on the RS physical mechanisms. For filamentary conduction, which is related to the creation and destruction of conduction paths (conventionally designated as conductive filaments, CFs), the two main device types are those whose CFs are formed by dielectric regions with a high concentration of oxygen vacancies (known as valence change memories [23,28]), and those where the CFs are formed by paths rich in metallic atoms, which migrate from an active electrode. We consider here this latter type of devices, including atomic layer deposition-grown HfO₂ dielectrics [29] that show filamentary conduction of metallic-like CFs [30,31]. The random nature of the CF formation leads to a strong variability [32,33], although techniques for controlling the CF size and location are subjects of research [32]. The CF temperature is critical to trigger the physical mechanisms behind RS [31]. Determining this temperature is a complicated issue both from the experimental [34] and theoretical [35] perspective. Although some measurements have been performed on hot spots in the electrodes, the key temperature for correctly describing the RS characteristics is at the CF narrowing [35], where Joule effects are higher and where, in general, the CF rupture takes place. In this respect, indirect strategies combining measurements with simulations are performed (mostly in the reset process, the transition from the LRS to the HRS, when the CF is broken) [34,36]. In order to deepen understanding of the issue, we present here a study to characterize the CF temperature and understand the role of this essential magnitude.

This manuscript is addressed as follows: in Section 2, we introduce the experimental details; in Section 3, the simulations are described; and in Section 4 the main results obtained are presented. Finally, the conclusions are drawn in Section 5.

2. Device Fabrication and Measurement Setup

The devices, based on the Ni/HfO₂/Si stack, were fabricated on (100) n-type CZ silicon wafers (resistivity 0.007–0.013 Ω cm); see the schematics in Figure 1a [29]. The HfO₂ dielectric layer (10 nm-thick) was grown by atomic layer deposition at 225 °C, using tetrakis (Dimethylamido)-hafnium (TDMAH) and H₂O as a precursor, and the carrier and purge gas was N₂. The top metal electrode (Ni with a 200 nm thickness) was deposited by magnetron sputtering and patterned by lift off. The device area was 15 µm × 15 µm.

The current–voltage (I-V) measurements were performed with a HP-4155B semiconductor parameter analyzer (Hewlett Packard, Palo Alto, California, United States). A negative voltage was applied to the top Ni electrode and the Si substrate was grounded. Successive I-V measurements for long RS series were obtained; the I-V meter was connected to the computer via GPIB (General Purpose Instrumentation Bus) and controlled using MATLAB (Matlab2020, Mathworks Inc, Natick, Massachusetts, United States). This allows us to automatically detect the reset current drop and subsequently stop the voltage ramp. Notice that a current compliance of 100 µA was employed during the set process. A total of 1800 successive RS cycles were measured; some I-V curves are shown in Figure 1a. The set and reset voltages and currents are plotted versus cycle number in Figure 1b–e. The cumulative distribution functions of the set and reset voltages are plotted in Figure 1f. The set and reset voltage were calculated by detecting current differences as described in MS2 and MR2 techniques in [37].

3. Device Simulation and Conductive Filament Temperature Determination

The simulation developed here is based on a finite difference 3D simulation domain of the memory cells described in Section 2, where the current and temperature are calculated accurately by solving the corresponding differential equations in a homogeneous approach of the materials included. One or several conductive filaments can be included in the simulation with cylindrical or truncated-cone shapes, whose geometries are calculated at every simulation step by considering the RS kinetics.

3.1. Simulator Description

The simulator describes the device electrical characteristics and the RS dynamics. The electrodes (we include 10 nm thick regions next to the dielectric) have been incorporated in the simulation domain (SD), which includes the dielectric. The grid consists of a set of 300 × 300 × 240 nodes. A uniform mesh with grid mesh distance of 0.125 nm was employed (the Ni atom radius approximately).

The 3D heat equation (Equation (1)) is solved to describe the device thermal distribution. Its solution is achieved by means of a fully explicit finite difference method [38]:

(1)$\dot{q}=-\nabla ·\left[k_{th}\left(x,y,z\right)\nabla T\left(x,y,z\right)\right]$

where T(x,y,z) is the temperature at each SD point, k_th(x,y,z) is the thermal conductivity, and $\dot{q}$ stands for the energy generated per unit time and volume. Dirichlet boundary conditions were used at the outer electrode layer surfaces (room temperature was fixed at these outer points, a reasonable assumption taking the high electrode thermal conductivity into account); perfectly matched layers (PML) were used at the SD lateral faces [39]. The CF is assumed to be a truncated cone [40] with metallic-like conduction properties (the electric conductivity was 3 × 10⁵ (Ω m)⁻¹ in line with values reported in previous works [41]). Joule heating takes place at the CF since the current is assumed to flow through the CF until it is ruptured [42]. The device series resistances are also included in the simulation tool. The heat generation rate ($\dot{q}$) is calculated by means of the electrical conductivity and the electric field distribution in the CF, where a linear increase of the resistivity is assumed as a consequence of the temperature rise (the temperature coefficient is taken as α_T = 0.0005 K⁻¹, as explained below). Three-dimensional thermal conductivities are employed in the electrodes (k_th(silicon) = 148 W/(m K), k_th(Ni) = 90 W/(m K)). The CF thermal conductivity was (k_th(CF) = 11 W/(m K)), a reasonable value according to ref. [31]. For the oxide thermal conductivity, we use k_th(HfO₂) = 1.0 W/(m K), which is in line with the values reported in [43,44]. The numerical solution of Equation (1) was developed by means of the weighted residual method [45] in a particular derivation known as the control-volume formulation.

The CF radii evolve following Equation (2), where an average Arrhenius-like mechanism is assumed to control the variation of the high-concentration regions of metallic atoms that shape the CF and produce the set and reset processes [46]:

(2)$\frac{dr\left(z\right)}{dt}=\pm A·e^{-\frac{E_a}{kT\left(z\right)}}$

where r(z) stands for the CF radius at the z coordinate, A is a fitting preexponential constant, k is the Boltzmann constant, and E_a is the activation energy of the main physical mechanism behind the CF variation (we assume that the mechanism modeled in Equation (2) has the strongest influence in the CF kinetics; it could also be seen as a model that averages different mechanisms involved).

A summary of the simulation parameters is provided in Table 1.

In each CF, a module is included to account for quantum effects due to a lateral filament constriction. These effects are modeled according to the quantum point contact (QPC) theory [47,48]. The appropriateness of this model, and the limitations and approximations needed to reach its final analytical form are discussed in depth in [49]. The QPC model current can be calculated as follows (Equation (3)) [47,48]:

(3)$I=\frac{2eN}{h}\left\{e{V}_{QPC}+\frac{1}{\alpha }ln\left[\frac{1+e^{\alpha \left(\Phi -\beta e{V}_{QPC}\right)}}{1+e^{\alpha \left(\Phi +\left(1-\beta \right)e{V}_{QPC}\right)}}\right]\right\}$

where Φ is assumed to be the potential barrier height measured with respect to the Fermi level, α is a parameter linked to the potential barrier thickness at the Fermi level, V_QPC is the voltage that drops at the sides of the CF constriction (in a fraction of β and (1 − β), as suggested in [47]), e is the elementary electron charge, I is the CF current, and N is the number of active channels in the CF [47,48]. Accordingly, the constriction voltage drop, V_QPC, is equal to the externally applied voltage to the device, V_app, minus the voltage drop in the rest of the CF, V_R (R stands for the CF resistance; it is an ohmic component). Notice that due to this and to the role of the series resistance linked to the electrodes, the resistance of the devices would be much higher than the contribution of the QPC model, which could be in some cases (very low barrier heights and N = 1) equal to 1/G₀. Therefore, for our simulator the following equation stands for the I-V curve:

(4)$V_{QPC}=V_{app}-V_R=V_{app}-I_{RRAM} R_{CF}$

where I_RRAM is the device current and R_CF is the filament resistance. We simulated several I-V reset curves to assess the influence of the different components contributing to the current. For the sake of simplicity, we consider voltage absolute values henceforth. In Figure 2, the total current is plotted in solid lines, while the QPC current component (i.e., the QPC current assuming a null R_CF) is shown in dashed lines (the QPC parameters are similar for all the curves shown). At low voltages, the I-V curve is mainly influenced by the QPC component; however, as the CF resistance rises, the ohmic component role increases, and the total current drops in comparison to the isolated QPC current component. Note that as the CF radius rises (a cylindrical CF shape is assumed here), the ohmic component influence decreases. As the current increases, the V_QPC weight with respect to V_R in the total device voltage (V_app) changes (see the inset in Figure 2). We simulated three different reset I-V curves for similar devices with cylindrical CFs with the following radii: 1 nm, 2 nm, and 3 nm. The I-V curves are identified as cycles #1, #2, and #3, respectively.

The higher the CF radius, the lower the CF resistance. Notice that our model works well prior to the reset event; at this point, the CF is broken and there is an abrupt current decrease until a value that corresponds to charge conduction across the dielectric between the remaining filament tip and the electrode. The CF average temperature obtained for the simulated curves is shown in Figure 3.

See in Figure 2 that the reset voltage increases with the CF radius. A slightly higher temperature is obtained for higher radii due to the current increase (higher Joule effects), although the difference is not significant. That is why the approximation followed in simpler modeling approaches, such as those based on circuit breaker networks, employs a threshold value for the temperature that triggers the formation/rupture of the conductive filaments [50,51].

3.2. Experimental Conductive Filament Temperature Extraction

The structure we simulate is shown in Figure 4a, where R_t and R_b stand for the CF top (Ni/HfO₂ interface) and bottom (Si-n+/HfO₂ interface) radii. Here, we obtain the temperature at each point of the simulation domain (Equation (1)); however, these data cannot be determined experimentally [34]. Therefore, a single temperature value is associated to the CF for each applied voltage for modeling purposes, which can be employed in simulators based on circuit breakers and in compact models. To shed light on this issue, a methodology to estimate the average conductive filament temperature is proposed, following [36]. A different perspective, although related to the one reported in [36], could also be employed for the average CF temperature extraction [52]. We attribute the CF resistance change in the low-voltage part of the reset I-V curves to the CF temperature increase (the CF shape is assumed to be fixed at these temperatures); see Equation (5) for the resistivity which determines the CF resistance for a fixed CF volume (in the LRS, we neglect charge conduction outside the CF):

(5)${\rho }_{CF}\left(T\right)={\rho }_{CF0}\left[1+{\alpha }_T\left(T-T_0\right)\right]$

Since we have a current point for each applied voltage, at most, we can estimate a CF temperature derived from the device resistance reduction. A correction to Equation (5) was proposed, adding a coefficient to account for the CF temperature nonuniformity, ${\rho }_{CF}\left(T\right)={\rho }_{CF0}\left[1+\gamma {\alpha }_T\left(T-T_0\right)\right]$, with γ = 2/3 for a cylindrical CF [53]. The associated resistance can be calculated for truncated-shaped CFs and can consequently extract the CF temperature.

We first need the temperature coefficient that can be estimated by comparing experimental with simulation data, assuming a device such as the one described in Figure 4a. The QPC component was extracted from the simulation data and the experimental measurements and the ohmic component was analyzed (and compared) in both cases. Since the CF shape is supposed to be invariant until the last portion of the I-V curve, close to the reset voltage [53], the resistance variation is associated to thermal effects [35] (Figure 4b). In this manner, we are able to determine the temperature coefficient (α_T = 0.0005 K⁻¹) that works well in our simulation tool for the experimental data and the models we are considering here (we fitted the lower part of the I-V curve that presents a low temperature due to the low currents associated).

See a detailed CF thermal distribution along the dielectric length (Figure 4c). An average temperature was calculated for each CF slice along the CF length to plot this figure. A temperature cross-section in the X-Z planes is shown in Figure 4d. Nevertheless, with the experimental I-V curve, we just can obtain one CF temperature datum for each voltage point in the I-V curve.

4. Results and Discussion

We obtained the CF temperature by simulating I-V curves and fitting several experimental curves (see Figure 5a). In each case, the QPC model parameters and the CF shape were tuned. The ohmic resistance (R_CF) component was extracted and plotted separately (Figure 5b); the simulated CF mean temperature was also calculated (Figure 5c). An average was calculated with the point-to-point distribution in the filament. Assuming the CF shape fitted in Figure 5a, R_CF was calculated, and the experimental CF temperature (using Equation (5)) could be estimated (see the dashed lines in Figure 5d). See that the extracted temperature is closer to the CF maximum temperature (plotted in Figure 5d) than to the CF mean temperature (Figure 5c).

This result makes sense since the temperature at the CF narrowing (where the higher temperatures are produced by the current lines funneling) determines the CF rupture and formation that triggers the reset and set processes. We also calculated the temperature following Ref. [52] and found no significant differences with the results plotted in Figure 5d. As shown in Figure 5, the key CF temperature to consider from the compact modeling viewpoint is the maximum one found in the detailed simulation distribution. Therefore, the thermal resistances and capacitances to model the device temperature [35], which is assumed to be the CF temperature, have to be carefully chosen.

5. Conclusions

A new procedure to determine the temperature in RRAM conductive filaments is presented. We make use of experimental data of unipolar devices based on the Ni/HfO₂/Si-n+ stack to estimate the operation temperature and the temperature coefficient of the device resistivity. A 3D RRAM simulator is developed that allows for the obtaining of the temperature distribution in the device’s active parts, in particular, in the conductive filaments that are created and ruptured to allow resistive switching. The CF temperature extracted is close to the maximum temperatures obtained by simulation at the CF narrowest sections. This temperature information is essential for the compact modeling of these emerging devices.

Author Contributions

Conceptualization, J.B.R., C.A.-P. and D.M.; software, C.A.-P., E.M.; data curation, F.J.-M., M.B.G. and F.C.; experimentation, M.B.G., F.C.; writing—original draft preparation, J.B.R., C.A.-P.; writing—review and editing, F.C., F.J.-M., D.M., M.B.G., E.M.; All authors have read and agreed to the published version of the manuscript.

Data Availability Statement

The data presented in this study are available on request from the corresponding author.

Conflicts of Interest

The authors declare no conflict of interest.

Footnotes

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Figures and Table

Figure 1. (a) Some experimental I-V curves of the devices under study for 1800 successive RS cycles in a long series depicting the set and reset voltages. The device structure is shown in the inset. (b) Set current, (c) set voltage, (d) reset current, (e) reset voltage versus cycle number, (f) cumulative distribution functions for the set and reset voltages.

Figure 2. Simulated current versus voltage and description of the different components; see the voltage components in the inset (VQPC + VR = Vapp). Three CF radii are considered (1 nm, 2 nm, 3 nm) for cycles #1, #2, and #3 (inset: voltage curves for cycle #1). The QPC parameters are: α = 15 eV−1, β = 0.55, Φ = 0.26 eV, N = 2.

Figure 3. (a) Average CF temperature along the simulated I-V curves during the reset process versus the device applied voltage, (b) average CF temperature versus VR. Three CF radii are considered (1 nm, 2 nm, 3 nm) for cycles #1 (orange line), #2 (blue line), and #3 (black line).

Figure 4. (a) Device schematic for the 3D simulations, (b) experimental ohmic I-V curve and simulated current for different temperature coefficients, (c) temperature distribution along the CF axis for Vapp = 1.74 V (0 < z < 10 nm corresponds to the Ni electrode (the CF/top electrode interface is placed at z = 10 nm)); the dielectric corresponds to 10 nm < z < 20 nm and the CF/bottom electrode interface is found at z = 20 nm. The maximum temperature is found in the [14 nm, 15 nm] interval due to the CF shape assumed, with the lower radius at the Ni/dielectric interface. (d) Three-dimensional temperature plot at the maximum temperature plane in the Y axis (inset: contour plot of the temperature distribution for the same X-Z axes cross-section).

Figure 5. (a) Experimental (dashed lines) and simulated (solid lines) I-V curve of the devices under study. Truncated cone CFs of different radii are employed (radii: Sim #1 Rt = 0.875 nm, Rb = 1.75 nm; Sim #2 Rt = 1.75 nm, Rb = 2.25 nm y; Sim #3 Rt = 1.50 nm, Rb = 2.25 nm). (b) Ohmic resistance extracted for the simulated reset curve (inset: schema of the model employed and ohmic resistance vs. VR), (c) average CF temperature at each I-V point along the simulated curve (inset: average CF temperature versus VR), (d) simulated CF maximum temperature and the CF temperature (dashed lines) obtained experimentally with a process in line with Ref. [53].

Table 1

Physical parameters used in the simulations.

αT	0.5 × 10−3 K−1	CF thermal parameter
kth(Si)	148 W K−1 m−1	Si thermal conductivity
kth(CF)	11 W K−1 m−1	CF thermal conductivity
kth(Ni)	90 W K−1 m−1	Ni thermal conductivity
kth(HfO2)	1 W K−1 m−1	HfO2 thermal conductivity
σσCF0	3 × 105 Ω−1 m−1	CF electrical conductivity
T 0	300 K	Room temperature
Ea	0.84 eV	Activation energy

References

1. Lanza, M.; Sebastian, A.; Lu, W.; Le Gallo, M.; Chang, M.-F.; Akinwande, D.; Puglisi, F.; Alshareef, H.; Liu, M.; Roldan, J. Memristive technologies for data storage, computation, encryption and radio-frequency communication. Science; 2022; 376, 6597. [DOI: https://dx.doi.org/10.1126/science.abj9979] [PubMed: https://www.ncbi.nlm.nih.gov/pubmed/35653464]

2. Spiga, S.; Sebastian, A.; Querlioz, D.; Rajendran, B. Memristive Devices for Brain-Inspired Computing; Elsevier: Amsterdam, The Netherlands, 2020.

3. Chou, C.-C.; Lin, Z.-J.; Tseng, P.-L.; Li, C.-F.; Chang, C.-Y.; Chen, W.-C.; Chih, Y.D.; Chang, T.-Y.J. An N40 256K×44 embedded RRAM macro with SL-precharge SA and Low-Voltage Current Limiter to Improve Read and Write Performance. Proceedings of the 2018 IEEE International Solid–State Circuits Conference; San Francisco, CA, USA, 11–15 February 2018.

4. Yang, C.-F.; Wu, C.-Y.; Yang, M.-H.; Wang, W.; Yang, M.-T.; Chien, T.-C.; Fan, V.; Ts, S.-C. Industrially applicable read disturb model and performance on Mega-bit 28nm embedded RRAM. Proceedings of the 2020 IEEE Symposium on VLSI Technology; Honolulu, HI, USA, 16–19 June 2020.

5. Wang, Q.; Zhang, D.; Zhao, Y.; Liu, C.; Xu, X.; Yang, J.; Lv, H. A 22nm 96K×144 RRAM macro with a self-tracking reference and a low ripple charge pump to achieve a configurable read window and a wide operating voltage range. Proceedings of the 2020 IEEE Symposium on VLSI Technology; Honolulu, HI, USA, 16–19 June 2020.

6. Yu, S.; Jiang, H.; Huang, S.; Peng, X.; Lu, A. A 3.6 Mb 10.1 Mb/mm2 embedded non-volatile Re-RAM macro in 22nm FinFET technology with adaptive forming/set/reset schemes yielding down to 0.5 V with sensing time of 5ns at 0.7 V. Proceedings of the IEEE International Solid–State Circuits Conference; San Francisco, CA, USA, 17–21 February 2019.

7. Sebastian, A.; Le Gallo, M.; Khaddam-Aljameh, R. Memory devices and applications for in-memory computing. Nat. Nanotechnol.; 2020; 15, pp. 529-544. [DOI: https://dx.doi.org/10.1038/s41565-020-0655-z] [PubMed: https://www.ncbi.nlm.nih.gov/pubmed/32231270]

8. Yu, S.; Jiang, H.; Huang, S.; Peng, X.; Lu, A. Computing-in-memory chips for deep learning: Recent trends and prospects. IEEE Circuits Syst. Mag.; 2021; 21, pp. 31-56. [DOI: https://dx.doi.org/10.1109/MCAS.2021.3092533]

9. Pérez-Bosch, E.; Romero-Zaliz, R.; Pérez, E.; Kalishettyhalli, M.; Reuben, J.; Schubert, M.; Jiménez-Molinos, F.; Roldán, J.; Wenger, C. Toward reliable compact modeling of multilevel 1T-1R RRAM devices for neuromorphic systems. Electronics; 2021; 10, 645. [DOI: https://dx.doi.org/10.3390/electronics10060645]

10. Zidan, M.; Strachan, J.; Lu, W.D. The future of electronics based on memristive systems. Nat. Electron.; 2018; 1, pp. 22-29. [DOI: https://dx.doi.org/10.1038/s41928-017-0006-8]

11. Prezioso, M.; Merrikh-Bayat, F.; Hoskins, B.; Adam, G.; Likharev, K.; Strukov, D. Training and operation of an integrated neuromorphic network based on metal-oxide memristors. Nature; 2015; 521, pp. 61-64. [DOI: https://dx.doi.org/10.1038/nature14441]

12. Zhu, K.; Mahmoodi, M.; Fahimi, Z.; Xiao, Y.; Wang, T.; Bukvišová, K.; Kolíbal, M.; Roldan, J.; Perez, D.; Aguirre, F. et al. Memristors with initial low resistive state for efficient neuromorphic systems. Adv. Intell. Syst.; 2022; 4, 2200001. [DOI: https://dx.doi.org/10.1002/aisy.202200001]

13. Nandakumar, S.; Rajendran, B. Bio-mimetic synaptic plasticity and learning in a sub-500 mV Cu/SiO₂/W. Microelectron. Eng.; 2020; 226, 111290. [DOI: https://dx.doi.org/10.1016/j.mee.2020.111290]

14. Romero-Zaliz, R.; Perez, E.; Jiménez-Molinos, F.; Wenger, C.; Roldán, J. Study of quantized hardware deep neural networks based on resistive switching devices, conventional versus convolutional approaches. Electronics; 2021; 10, 346. [DOI: https://dx.doi.org/10.3390/electronics10030346]

15. Merolla, P.; Arthur, J.; Alvarez-Icaza, R.; Cassidy, A.; Sawada, J.; Akopyan, F.; Jackson, B.; Imam, N.; Guo, C.; Nakamura, Y.B. A million spiking-neuron integrated circuit with a scalable communication network and interface. Science; 2014; 345, pp. 668-673. [DOI: https://dx.doi.org/10.1126/science.1254642]

16. Roldan, J.B.; Maldonado, D.; Aguilera-Pedregosa, C.; Moreno, E.; Aguirre, F.; Romero-Zaliz, R.; García-Vico, A.; Shen, Y.; Lanza, M.; Yuan, Y. et al. Spiking neural networks based on two-dimensional materials. 2D Mater. Appl.; 2022; 26, 63. [DOI: https://dx.doi.org/10.1038/s41699-022-00341-5]

17. Yang, B.; Arumí, D.; Manich, S.; Gómez-Pau, A.; Rodríguez-Montañés, R.; Gonzalez, M.; Campabadal, F.; Fang, L. RRAM Random Number Generator Based on Train of Pulses. Electronics; 2021; 10, 1831. [DOI: https://dx.doi.org/10.3390/electronics10151831]

18. Wei, Z.; Katoh, Y.; Ogasahara, S.; Yoshimoto, Y.; Kawai, K.; Ikeda, Y.; Eriguchi, K.; Ohmori, K.; Yoneda, S. True random number generator using current difference based on a fractional stochastic model in 40-nm embedded ReRAM. Proceedings of the 2016 IEEE International Electron Devices Meeting (IEDM); San Francisco, CA, USA, 3–7 December 2016; [DOI: https://dx.doi.org/10.1109/IEDM.2016.7838349]

19. Lanza, M.; Wen, C.; Li, X.; Zanotti, T.; Puglisi, F.M.; Shi, Y.; Saiz, F.; Antidormi, A.; Roche, S.; Zheng, W. et al. Advanced data encryption using two-dimensional materials. Adv. Mater.; 2021; 33, 2100185.

20. Carboni, R.; Ielmini, D. Stochastic Memory Devices for Security and Computing. Adv. Electron. Mater.; 2019; 5, 1900198. [DOI: https://dx.doi.org/10.1002/aelm.201900198]

21. Chua, L.O.; Sung, M.K. Memristive devices and systems. Proc. IEEE; 1976; 64, pp. 209-223. [DOI: https://dx.doi.org/10.1109/PROC.1976.10092]

22. von Witzleben, M.; Fleck, K.; Funck, C.; Baumkötter, B.; Zuric, M.; Idt, A.; Breuer, T.; Waser, R.; Böttger, U.; Menzel, S. Investigation of the Impact of High Temperatures on the Switching Kinetics of Redox-Based Resistive Switching Cells using a High-Speed Nanoheater. Adv. Electron. Mater.; 2017; 3, 1700294. [DOI: https://dx.doi.org/10.1002/aelm.201700294]

23. Funck, C.; Menzel, S. Comprehensive model of electron conduction in oxide-based memristive devices. ACS Appl. Electron. Mater.; 2021; 3, pp. 3674-3692. [DOI: https://dx.doi.org/10.1021/acsaelm.1c00398]

24. Lanza, M.; Waser, R.; Ielmini, D.; Yang, J.; Goux, L.; Suñe, J.; Kenyon, A.; Mehonic, A.; Spiga, S.; Rana, V. et al. Standards for the Characterization of Endurance in Resistive Switching Devices. ACS Nano; 2021; in press [DOI: https://dx.doi.org/10.1021/acsnano.1c06980]

25. Chang, C.-C.; Chen, P.-C.; Chou, T.; Wang, I.-T.; Hudec, B.; Chang, C.-C.; Tsai, C.-M.; Chang, T.-S.; Hou, T.-H. Mitigating Asymmetric Nonlinear Weight Update Effects in Hardware Neural Network Based on Analog Resistive Synapse. IEEE J. Emerg. Sel. Top. Circuits Syst.; 2018; 8, pp. 116-124. [DOI: https://dx.doi.org/10.1109/JETCAS.2017.2771529]

26. Hirtzlin, T.; Bocquet, M.; Penkovsky, B.; Klein, J.-O.; Nowak, E.; Vianello, E.; Portal, J.-M.; Querlioz, D. Digital Biologically Plausible Implementation of Binarized Neural Networks with Differential Hafnium Oxide Resistive Memory Arrays. Front. Neurosci.; 2020; 13, 1383. [DOI: https://dx.doi.org/10.3389/fnins.2019.01383]

27. Camuñas-Mesa, A.; Vianello, E.; Reita, C.; Serrano-Gotarredona, T.; Linares-Barranco, B. A CMOL-Like Memristor-CMOS Neuromorphic Chip-Core Demonstrating Stochastic Binary STDP. IEEE J. Emerg. Sel. Top. Circuits Syst.; 2022; 12, pp. 898-912. [DOI: https://dx.doi.org/10.1109/JETCAS.2022.3207514]

28. Aldana, S.; García-Fernández, P.; Romero-Zaliz, R.; González, M.; Jiménez-Molinos, F.; Gómez-Campos, F.; Campabadal, F.; Roldán, J. Resistive Switching in HfO2 based valence change memories, a comprehensive 3D kinetic Monte Carlo approach. J. Phys. D Appl. Phys.; 2020; 53, 225106. [DOI: https://dx.doi.org/10.1088/1361-6463/ab7bb6]

29. Gonzalez, M.; Rafí, J.; Beldarrain, O.; Zabala, M.; Campabadal, F. Analysis of the switching variability in Ni/HfO2-based RRAM devices. IEEE Trans. Dev. Mat. Reliab.; 2014; 14, pp. 769-771.

30. Ielmini, D.; Waser, R. Resistive Switching: From Fundamentals of Nanoionic Redox Processes to Memristive Device Applications; Wiley-VCH: Hoboken, NJ, USA, 2015.

31. Aldana, S.; García-Fernández, P.; Rodríguez-Fernández, A.; Romero-Zaliz, R.; González, M.; Jiménez-Molinos, F.; Campabadal, F.; Gómez-Campos, F.; Roldán, J. A 3D Kinetic Monte Carlo simulation study of Resistive Switching processes in Ni/HfO2/Si-n+-based RRAMs. J. Phys. D Appl. Phys.; 2017; 50, 335103. [DOI: https://dx.doi.org/10.1088/1361-6463/aa7939]

32. Spring, J.; Sediva, E.; Hood, Z.; Gonzalez-Rosillo, J.; O’Leary, W.; Kim, K.; Carrillo, A.; Rup, J.L.M. Toward Controlling Filament Size and Location for Resistive Switches via Nanoparticle Exsolution at Oxide Interfaces. Nano-Micro Small; 2020; 16, 2003224. [DOI: https://dx.doi.org/10.1002/smll.202003224] [PubMed: https://www.ncbi.nlm.nih.gov/pubmed/32939986]

33. Simanjuntak, F.; Chandrasekaran, S.; Lin, C.; Tseng, T.-Y. Switching Failure Mechanism in Zinc Peroxide-Based Programmable Metallization Cell. Nanoscale Res. Lett.; 2018; 13, 327. [DOI: https://dx.doi.org/10.1186/s11671-018-2743-7]

34. Deshmukh, S.; Muñoz-Rojo, M.; Yalon, E.; Vaziri, S.; Koroglu, C.; Islam, R.; Iglesias, R.; Saraswat, K.; Pop, E. Direct measurement of nanoscale filamentary hot spots in resistive memory devices. Sci. Adv.; 2022; 8, eabk1514. [DOI: https://dx.doi.org/10.1126/sciadv.abk1514]

35. Roldán, J.B.; González-Cordero, G.; Picos, R.; Miranda, E.; Palumbo, F.; Jiménez-Molinos, F.; Moreno, E.; Maldonado, D.; Baldomá, S.; Al Chawa, M.M. et al. On the Thermal Models for Resistive Random Access Memory Circuit Simulation. Nanomaterials; 2021; 11, 1261. [DOI: https://dx.doi.org/10.3390/nano11051261]

36. Russo, U.; Ielmini, D.; Cagli, C.; Lacaita, A.L. Self-Accelerated Thermal Dissolution Model for Reset Programming in Unipolar Resistive-Switching Memory (RRAM) Devices. IEEE Trans. Electron Devices; 2009; 56, pp. 193-200. [DOI: https://dx.doi.org/10.1109/TED.2008.2010584]

37. Maldonado, D.; Aldana, S.; González, M.; Jiménez-Molinos, F.; Campabadal, F.; Roldán, J. Parameter extraction techniques for the analysis and modeling of resistive memories. Microelectron. Eng.; 2022; 265, 111876. [DOI: https://dx.doi.org/10.1016/j.mee.2022.111876]

38. Mazumder, S. Numerical Methods for Partial Differential Equations: Finite Difference and Finite Volume Methods; Academic Press: Cambridge, MA, USA, 2015.

39. Moreno, E.; Hemmat, Z.; Roldan, J.; Pantoja, M.; Bretones, A.; Garcia, S.; Faez, R. Implementation of Open Boundary Problems in Photo-Conductive Antennas by Using Convolutional Perfectly Matched Layers. IEEE Trans. Antennas Propag.; 2016; 64, pp. 4919-4922. [DOI: https://dx.doi.org/10.1109/TAP.2016.2602357]

40. Pan, F.; Gao, S.; Chen, C.; Song, C.; Zeng, F. Recent progress in resistive random access memories: Materials, switching mechanisms and performance. Mater. Sci. Eng.; 2014; 83, pp. 1-59. [DOI: https://dx.doi.org/10.1016/j.mser.2014.06.002]

41. Huang, P.; Liu, X.Y.; Chen, B.; Li, H.T.; Wang, Y.J.; Deng, Y.X.; Kang, J.F. A Physics-Based Compact Model of Metal-Oxide-Based RRAM DC and AC Operations. IEEE Trans. Electron Devices; 2013; 60, pp. 4090-4097. [DOI: https://dx.doi.org/10.1109/TED.2013.2287755]

42. Ielmini, D.; Nardi, F.; Balatti, S. Evidence for Voltage-Driven Set/Reset Processes in Bipolar Switching RRAM. IEEE Trans. Electron Devices; 2012; 59, pp. 2049-2056. [DOI: https://dx.doi.org/10.1109/TED.2012.2199497]

43. Scott, E.; Gaskins, J.; King, S.; Hopkins, P. Thermal conductivity and thermal boundary resistance of atomic layer deposited high- k dielectric aluminum oxide, hafnium oxide, and titanium oxide thin films on silicon. APL Mater.; 2018; 6, 058302. [DOI: https://dx.doi.org/10.1063/1.5021044]

44. Panzer, M.; Shandalov, M.; Rowlette, J.; Oshima, Y.; Chen, Y.; McIntyre, P.; Goodson, K. Thermal Properties of Ultrathin Hafnium Oxide Gate Dielectric Films. IEEE Electron Device Lett.; 2009; 30, pp. 1269-1271. [DOI: https://dx.doi.org/10.1109/LED.2009.2032937]

45. Finlayson, B. The Method of Weighted Residuals and Variational Principles: With Application in Fluid Mechanics, Heat and Mass Transfer; Academic Press: Cambridge, MA, USA, 1972.

46. Ielmini, D. Modeling the universal set/reset characteristics of bipolar RRAM by field- and temperature-driven filament growth. IEEE Trans. Electron Devices; 2011; 58, pp. 4309-4317. [DOI: https://dx.doi.org/10.1109/TED.2011.2167513]

47. Miranda, E.; Walczyk, C.; Wenger, C.; Schroeder, T. Model for the resistive switching effect in HfO2 MIM structures based on the transmission properties of narrow constrictions. IEEE Electron. Device Lett.; 2010; 31, 609. [DOI: https://dx.doi.org/10.1109/LED.2010.2046310]

48. Roldán, J.; Miranda, E.; González-Cordero, G.; García-Fernández, P.; Romero-Zaliz, R.; González-Rodelas, P.; Aguilera, A.; González, M.; Jiménez-Molinos, F. Multivariate analysis and extraction of parameters in resistive RAMs using the Quantum Point Contact model. J. Appl. Phys.; 2018; 123, 014501. [DOI: https://dx.doi.org/10.1063/1.5006995]

49. Milano, G.; Aono, M.; Boarino, L.; Celano, U.; Hasegawa, T.; Kozicki, M.; Majumdar, S.; Menghini, M.; Miranda, E.; Ricciardi, C. et al. Quantum Conductance in Memristive Devices: Fundamentals, Developments, and Applications. Adv. Mater; 2022; 34, 2201248. [DOI: https://dx.doi.org/10.1002/adma.202201248]

50. Chang, S.; Lee, J.; Chae, S.; Lee, S.; Liu, C.; Kahng, B.; Kim, D.; Noh, T. Occurrence of both unipolar memory and threshold resistance switching in a NiO film. Phys. Rev. Lett.; 2009; 102, 026801. [DOI: https://dx.doi.org/10.1103/PhysRevLett.102.026801] [PubMed: https://www.ncbi.nlm.nih.gov/pubmed/19257301]

51. Brivio, S.; Spiga, S. Stochastic circuit breaker network model for bipolar resistance switching memories. J. Comput. Electron.; 2017; 16, pp. 1154-1166. [DOI: https://dx.doi.org/10.1007/s10825-017-1055-y]

52. Zhuang, P.; Ma, W.; Liu, J.; Cai, W.; Lin, W. Progressive RESET induced by Joule heating in hBN RRAMs. Appl. Phys. Lett.; 2021; 118, 143101. [DOI: https://dx.doi.org/10.1063/5.0040902]

53. Russo, U.; Ielmini, D.; Cagli, C.; Lacaita, A.L. Filament conduction and reset mechanism in NiO-based resistive switching memory (RRAM) Devices. IEEE Trans. Electron Devices; 2009; 56, pp. 186-192. [DOI: https://dx.doi.org/10.1109/TED.2008.2010583]