High-density vertical sidewall MoS2 transistors through T-shape vertical lamination

Abstract

Vertical transistors, in which the source and drain are aligned vertically and the current flow is normal to the wafer surface, have attracted considerable attention recently. However, the realization of high-density vertical transistors is challenging, and could be largely attributed to the incompatibility between vertical structures and conventional lateral fabrication processes. Here we report a T-shape lamination approach for realizing high-density vertical sidewall transistors, where lateral transistors could be pre-fabricated on planar substrates first and then laminated onto vertical substrates using T-shape stamps, hence overcoming the incompatibility between planar processes and vertical structures. Based on this technique, we vertically stacked 60 MoS₂ transistors within a small vertical footprint, corresponding to a device density over 10⁸ cm⁻². Furthermore, we demonstrate two approaches for scalable fabrication of vertical sidewall transistor arrays, including simultaneous lamination onto multiple vertical substrates, as well as on the same vertical substrate using multi-cycle layer-by-layer laminations.

Vertical transistors based on 2D semiconductors have the potential to reduce the footprint of electronic circuits, but their high-density integration remains challenging. Here, the authors report a vertical lamination approach for realizing high-density MoS₂ vertical sidewall transistors.