1. Introduction
As is well known, chaotic laser signals are highly sensitive to system initial conditions and external disturbances, exhibiting a high degree of randomness. Currently, they are widely applied in various fields such as chaotic laser radar, physical random numbers, chaotic neural networks, image recognition and encryption and optical reservoir computing [1,2,3,4,5,6,7,8]. Moreover, they also have potential applications in chaos computing.
Compared with the transmission capacity of optical chaotic networks, the switching capacity of them is still relatively weak. At present, dynamic packet switching technology for optical chaotic signals is an effective measure to enhance the switching capability of optical chaotic networks. The foundation for developing dynamic packet switching technology is to achieve optical chaotic signal processing such as multiplexing, demultiplexing, switching, regeneration and storage involved in optical chaotic signal packet switching nodes. However, the prerequisite for achieving the above chaotic signal processing is to develop low-power, low-loss and high-speed optical chaos computing. Therefore, chaos computing has attracted the great interest of many scholars.
Vertical-cavity surface-emitting lasers (VCSELs), as a microchip semiconductor laser, exhibit many advantages over edge-emitting lasers, in some areas such as low threshold current, single longitudinal mode operation, high modulation frequency, low cost and large-scale integration into two-dimensional arrays [9,10,11]. When VCSELs are subjected to optical injection or optical feedback, they easily generate chaotic x-PC and chaotic y-PC which are orthogonal to each other [12,13,14,15,16,17,18,19,20,21]. The dynamic behaviors such as polarization switching and polarization bistability in VCSELs can be induced by changing the pump current, the strength of the injected light or the detuning of the injected light [22,23,24,25,26]. Therefore, based on the high-dimensional chaotic system of VCSELs, optical chaotic logic operations with different functions can be designed and implemented by using its rich polarization modes.
In recent years, research in chaos computing has primarily focused on nanosecond-scale basic computations, with very few studies at the picosecond scale. For example, based on a VCSEL with tunable optical injection and polarization bistability, C Masoller et al. implemented an all-optical stochastic logic gate [9,10,11]. Based on electro-optic (EO) modulation theory and the VCSEL subjected to external optical injection, Zhong et al. achieved optoelectronic composite logic gates such as AND, NAND, OR, NOR, XOR and XNOR [25]. Based on chaos synchronization theory, Yan implemented all-optical logic gates [12]. Our previous works focused on reconfigurable chaotic logic operations [27,28]. The above implementation of chaotic logic gates almost lacks error detection and correction capabilities. However, the development of more complex combinational chaotic logic operations, such as optical chaotic data selection, is still relatively lagging behind, and few people pay attention to it. In 2019, using the polarization bistability in a VCSEL injected by a sampled grating distributed Bragg reflector laser, Zhong et al. first implemented picosecond-level optical chaotic data selection logic operations, and the operation speed was up to 10 Gb/s [29]. In Zhong’s scheme, the main reasons limiting the operational speed and noise resistance are twofold: insufficient mutual inhibition between x-PC and y-PC and the poor capability of the threshold demodulation mechanism for short bit durations. In the presence of significant noise, logic outputs may produce errors, but the scheme does not provide appropriate error detection and correction methods. Motivated by these issues, we propose a novel approach for achieving high-speed optical chaotic data selection logic operations with error detection and correction capabilities. In our approach, based on EO modulation theory, we achieve complete mutual inhibition between x-PC and y-PC. By employing an outstanding mean comparison demodulation mechanism, we enable the optical chaotic data selection logic operations to achieve a maximum speed of up to 114 Gb/s. Additionally, leveraging the generalized chaos synchronization theory, the system is capable of accurately detecting and correcting errors in chaotic logic outputs, with a noise strength limit as high as 185 dBw, exceeding the noise strength limit reported in reference [28] by approximately 100 dBw. These research results have great applications and reference values for the construction of high-speed optical chaos computing architecture and the development of optical chaotic network communication systems.
2. Theory and Model
Figure 1 depicts a detailed optical path diagram for implementing high-speed optical data selection logic operations. The optical isolator (IS) prevents feedback from the fiber polarization beam splitter (FPBS) into the laser. The fiber beam splitter (FBS) divides light into multiple beams. Meanwhile, the neutral density filter (NDF) controls light intensity. The Faraday rotator (FR) and half-wave plate (HWP) change the polarization direction of light. The optical amplifier (OA) boosts light power. Since the distributed feedback (DFB) laser can emit polarized light in any direction, to ensure that arbitrary polarized light from IS1 can be parallelly injected into the x-PC and y-PC of the master VCSEL (M-VCSEL), it is necessary to convert the arbitrary polarized light into linearly polarized light by some optical passive devices placed between the IS1 and the fiber coupler (FC1). Here, we consider that the converted linear polarization light is the x-PC. Arbitrarily polarized light from the DFB laser is split into x-PC and y-PC by the FPBS1. The y-PC is converted into x-PC by FR1 and HWP1, and then these two x-PCs are coupled into a single x-PC beam by the FC1. Arbitrarily polarized light emitted from the DFB laser is initially split into x-PC and y-PC, using the FPBS1. The y-PC is converted into x-PC through the use of FR1 and HWP1. Subsequently, these two x-PC beams are combined into a unified x-PC beam using FC1. The unified x-PC beam is divided into three separate beams using a 1 × 3 FBS1. The amplitudes of these beams are individually denoted as Einj1, Einj2 and Einj3. Each beam’s intensity is controlled by NDF1, NDF2 and NDF3, respectively. Here, the amplitudes Einj1 and Einj2 are modulated as optical logic inputs I1 and I2, respectively, while the amplitude Einj3 is modulated as the optical clock signal I3. The three beams of x-PC are combined into a single beam using FC2. This unified x-PC beam is then split into two separate x-PC beams using a 1 × 2 FBS2. One of these x-PC beams is directed into the M-VCSEL after passing through NDF4. The second x-PC beam is converted into y-PC using FR2 and HWP2, before being injected into the M-VCSEL following passage through NDF5. The polarized light emitted by the M-VCSEL is separated into x-PC and y-PC by the FPBS2 after transmission through the IS2. The x-PC, designated as o-light, is directly introduced into the periodic poled LiNbO3 (PPLN). Conversely, the y-PC, referred to as e-light, is directed into the PPLN after polarization conversion facilitated by FR3 and HWP3. Under the influence of the applied electric field EA, the PPLN exhibits the electro-optic effect. The o-light (x-PC) generated by the PPLN is directed into the S-VCSEL following amplification by OA1. Conversely, the e-light output is converted into y-PC using FR4 and HWP4, before being introduced into the slave VCSEL (S-VCSEL) subsequent to amplification by OA2. The time delay between the light emission from the PPLN to its arrival at the S-VCSEL is denoted as τ. Subsequently, the light emitted by the S-VCSEL undergoes polarization separation into x-PC and y-PC using FPBS3, following its transmission through the IS3. Here, the logic outputs O1 and O2 are derived by demodulating the xP-PC and yP-PC outputs from the PPLN and the xS-PC and yS-PC outputs from the S-VCSEL, respectively. The subscripts P and S denote the origins from the PPLN and S-VCSEL, respectively.
In our experimental setup, the applied electric field EA used to modulate the control logic signal C is a square wave signal characterized by distinct low and high levels, denoted as EA1 and EA2, respectively, i.e., C = 0 when EA = EA1, and C = 1 if EA = EA2. Under the appropriate conditions of EA and utilizing a suitable logic output demodulation mechanism, data selection logic operations can be effectively implemented, i.e., . According to the theory of generalized chaos synchronization, when the S-VCSEL undergoes strong light injection, its output polarization light exhibits high correlation with the polarization light emitted from the PPLN. Therefore, it is feasible to establish . This expression signifies the successful implementation of delay storage in data selection logic operations.
Under the influence of spontaneous emission noise, based on the SFM of VCSEL, the rate equation of M-VCSEL subjected to external optical injection can be expressed as follows:
(1)
(2)
(3)
(4)
In the above formulas, the subscript M represents M-VCSEL; the subscripts x and y represent x-PC and y-PC, respectively; N is the total carrier concentration, while n is the difference in concentration between carriers with spin-up and spin-down; E is the normalized amplitude, and , where g is the differential material gain; A is the slowly varying amplitude; γe is the nonradiative carrier relaxation rate; a is the linewidth enhancement factor; k is the field decay rate; γs is the spin-flip relaxation rate; γa is the linear dichroism; γp is the linear birefringence; μM is the normalized bias current of the M-VCSEL; denotes the noise term, with βsp being the spontaneous emission factor, and noise strength Noi = 10lg()2. ξx and ξy are two independent Gaussian white noises with a mean value of 0 and a variance of 1; kx and ky are the injection strength for x-PC and y-PC, respectively; is the sum of Einj1, Einj2 and Einj3, where Ainj is the slowly varying amplitude of the injected field; Δω = ωinj − ωref is the detuning between the frequency of the injected field and the reference frequency of the M-VCSEL; ωinj is the angular optical frequency of the injected field; the reference optical frequency ωref is defined as (ωx + ωy)/2, where ωx = −γp + aγa and ωy = γp − aγa are the optical frequency of the x-PC and the y-PC of the free-running VCSEL.
The x-PC and y-PC emitted by the M-VCSEL are injected into the PPLN as the initial input of the o-light and the e-light, respectively, so we have
(5)
where Uo and Ue are the amplitudes of the o-light and the e light, respectively; ℏ is the Planck constant; SA is the effective area of the light spot; V is the volume of the active layer of the VCSEL; vc is the light velocity in a vacuum; TL = 2ngυc/Lv refers to the round trip time in the laser cavity; Lv is the length of the laser cavity; ng is the effective refractive index of the laser active layer; ω0 is the central frequency of the M-VCSEL; n1 and n2 are the undisturbed refractive indices of the o-light and the e-light, respectively. With the phase mismatch and the weak second-order nonlinear effect, the analytical solutions of the wave coupling equations of the linear EO effect for the two PCs in the PPLN are written as follows:(6)
where L is the length of the PPLN; ρx,y, β0 and ϕx,y are presented in Ref. [30]. The amplitudes of xP-PC and yP-PC after undergoing electro-optic modulation in PPLN can be represented as follows:(7)
The rate equations for the S-VCSEL subjected to strong optical injection with a delay of τ can be represented as follows:
(8)
(9)
(10)
where the subscript S refers to the S-VCSEL; ∆ωS is the center frequency detuning between the M-VCSEL and the S-VCSEL; kinjx and kinjy are the injection strength of the xP-PC and yP-PC, respectively; μS is the normalized bias current of the S-VCSEL.3. Results and Discussions
We first calculate Equations (1)–(10) using the fourth-order Runge–Kutta method, employing the parameters listed in Table 1. Since the PPLN cannot generate chaotic polarized light, we investigate the influence of the applied electric field EA and the optical injection amplitude Einj on the dynamics of xS-PC and yS-PC outputs from the S-VCSEL, illustrated in Figure 2a,b. The figures demonstrate that within the parameter space defined by EA and Einj, xS-PC and yS-PC exhibit various typical dynamic states such as single-period oscillation (P1), two-period oscillation (P2), quasi-periodic oscillation (QP) and chaotic behavior (CO). Our focus here is specifically on the evolution of the chaotic state. From Figure 2a, it can be observed that xS-PC remains in a chaotic state within the regions corresponding to 0–42 kV/mm (EA) and 0.1–10 (Einj). As the EA varies from 42 kV/mm to 100 kV/mm, the chaotic state of xS-PC shows quasi-periodic variations with Einj. Specifically, xS-PC exhibits chaotic states when Einj falls within the ranges such as 0.18–0.23, 0.89–0.93, 1.59–1.64, 2.3–2.35 and 3.01–3.06, with a period of approximately 0.7. Figure 2b indicates that yS-PC is in a chaotic state across most regions corresponding to 0–42 kV/mm (EA) and 0.07–10 (Einj). As the EA varies from 42 kV/mm to 58 kV/mm, the chaotic state of yS-PC also exhibits quasi-periodic variations with Einj.
Based on the theory of generalized chaos synchronization, when the S-VCSEL experiences intense optical injection from the PPLN, significant correlations may arise between xP-PC and xS-PC, as well as between yP-PC and yS-PC. Here, the correlation coefficient ρx,y is introduced to quantify the magnitude of the correlation between these pairs:
(11)
where IPx,Py(t − τ) = |EPx,Py((t − τ))|2, ISx,Sy(t) = |ESx,Sy(t)|2 and the symbol < > denotes the time average. The correlation coefficient ρx,y ranges from 0 to 1, with higher values indicating a stronger correlation between the respective pairs.Here, we calculate the dependence of the correlation coefficient ρx,y on the optical injection amplitude Einj, as shown in Figure 3. Under the condition of EA = 11 kV/mm as depicted in Figure 3a, as Einj increases from 0 to 2.8, ρx gradually rises to 0.73. As Einj further increases to 4.2, ρx shows a declining trend, dropping from 0.73 to 0.41. With Einj increasing to 4.4, ρx rapidly rises from 0.41 to a peak of 0.97. As Einj progresses from 4.4 to 10, ρx slowly decreases to 0.84. For ρy, as Einj increases from 0 to 3.6, it swiftly rises from 0 to 0.82; with a further increase in Einj to 10, ρy decreases slowly to 0.45. From Figure 3b, it is observed that when EA = 25 kV/mm, the evolution curve of ρx with Einj closely matches that in Figure 3a. However, the evolution of ρy differs: as Einj increases from 0 to 3.6, ρy increases from 0 to 0.82; as Einj continues to 4.2, ρy decreases slowly to 0.77; then, as Einj rises from 4.2 to 4.4, ρy swiftly increases to a maximum of 0.98. Finally, as Einj progresses to 10, ρy decreases gradually from 0.98 to 0.9. In our approach, a stronger correlation is advantageous for enhancing the storage performance of data selection logic operations. Therefore, it is concluded that under the condition where the EA equals 11 kV/mm, ρx reaches a relatively high value around Einj = 4.4, peaking at 0.97. Similarly, ρy achieves a relatively high value around Einj = 3.6, reaching a maximum of 0.82. When the EA is 25 kV/mm and Einj approaches 4.4, both ρx and ρy reach relatively high values, with ρx peaking at 0.96 and ρy at 0.98.
To further determine the value range of Einj for modulating logic inputs, we calculate the evolutions of the polarization bistability of xP-PC, yP-PC, xS-PC and yS-PC under applied electric fields EA of 11 kV/mm and 25 kV/mm, respectively, as illustrated in Figure 4. From Figure 4a, it is evident that under an applied electric field EA of 11 kV/mm, when Einj ranges from 0 to 3.9, xP-PC predominates, while yP-PC is suppressed. However, the extent of mutual suppression between them is not pronounced. When Einj varies between 3.9 and 4.5, both xP-PC and yP-PC display bistable loops, accompanied by an increased degree of mutual suppression. When Einj ranges from 4.5 to 10, xP-PC dominates completely, while yP-PC is nearly entirely suppressed. In Figure 4b, when Einj is below 3.9, the evolution of the polarization bistability for xS-PC and yS-PC is similar to that observed in Figure 4a. When Einj ranges from 3.9 to 4.7, both xS-PC and yS-PC demonstrate bistable loops. As Einj exceeds 4.7, the mutual suppression between xS-PC and yS-PC intensifies, leading to the complete suppression of yS-PC by xS-PC. From Figure 4c, it is evident that under an applied electric field EA of 25 kV/mm, when Einj ranges from 0 to 3.9, yP-PC dominates, while xP-PC is suppressed. When Einj ranges from 3.9 to 4.7, both xP-PC and yP-PC exhibit bistable loops, with an increased degree of mutual suppression observed between them. When Einj ranges from 4.7 to 10, yP-PC dominates completely, while xP-PC is entirely suppressed. The polarization bistability evolutions of xS-PC and yS-PC depicted in Figure 4d closely resemble those observed in Figure 4c. In our scheme, the mean comparison mechanism is employed to demodulate xP-PC and yP-PC and xS-PC and yS-PC to obtain logic outputs O1 and O2 (as described below). The bit error rate of O1 and O2 is influenced by the extent of mutual suppression between xP-PC and yP-PC, as well as between xS-PC and yS-PC. A higher degree of mutual suppression correlates with a lower bit error rate. Therefore, based on the above analysis, it can be inferred that the value of Einj used for modulating the logic input should be greater than 4.7. Considering that maximizing the correlation coefficient ρx,y is desirable and ensuring that xS-PC and yS-PC maintain a chaotic state, we opt to choose appropriate values of Einj within the range of 5.35 to 5.46 for modulating the logic inputs.
Assume that the optical injection amplitude Einj is equal to the sum of three square wave signals, i.e., Einj = Einj1 + Einj2 + Einj3, where Einj1 and Einj2 are modulated as optical logic inputs I1 and I2, and Einj3 is modulated as an optical clock signal I3. Since the logic input can be either 0 or 1, there are eight possible input combinations: (0, 0, 0), (0, 0, 1), (0, 1, 0), (0, 1, 1), (1, 0, 0), (1, 0, 1), (1, 1, 0) and (1, 1, 1). Here, we modulate these eight input combinations using four-level signals EinjI, EinjII, EinjIII and EinjIV (where EinjI, EinjII, EinjIII and EinjIV are the four possible values of Einj). Specifically, EinjI denotes (0, 0, 0), EinjII represents (0, 0, 1), (0, 1, 0) and (1, 0, 0), EinjIII for (0, 1, 1), (1, 0, 1) and (1, 1, 0) and EinjIV for (1, 1, 1). In this case, the four-level signals remain constant during a bit duration T. Here, T is equal to 10 ps, which means the data selection logic operates at a speed of 100 Gb/s. We take EinjI = 5.37, EinjII = 5.4, EinjIII = 5.43 and EinjIV = 5.46, which means when Einj1, Einj2 and Einj3 are all equal to 1.79, I1, I2 and I3 are all equal to 0, and if Einj1, Einj2 and Einj3 are all equal to 1.82, I1, I2 and I3 are all equal to 1. Additionally, when EA = EA1 = 11 kV/mm, C = 1, and if EA = EA2 = 25 kV/mm, C = 0. The demodulation mechanism for the logic output is described as follows: Suppose that the duration of C being equal to 0 or 1, denoted as T1, is n’ times the bit duration T, i.e., T1 = n’T. During the time duration T1, the amplitude of xP-PC, yP-PC, xS-PC and yS-PC is sampled M times, where M is equal to T1/h, and h represents the sampling interval. Within T1, the average amplitudes of xP-PC, yP-PC, xS-PC and yS-PC are respectively denoted by APx, APy, ASx and ASy:
(12)
(13)
(14)
(15)
where EPx(j), EPy(j), ESx(j) and ESy(j) respectively represent the jth amplitude sampling value of xP-PC, yP-PC, xS-PC and yS-PC within T1. By comparing APx and APy, as well as ASx and ASy, we can determine the logic outputs O1 and O2 within T1. The demodulation rules are as follows: when APx > APy and ASx > ASy, O1 = O2 = 1; if APx ≤ APy and ASx ≤ ASy, then O1 = O2 = 0.We calculate the numerical values of APx, APy, ASx and ASy across different time intervals, as presented in Table 2. Figure 5 illustrates the optical data selection logic operations involving two identical logic outputs. Figure 5a depicts the relationship between the applied electric field EA and the optical injection amplitude Einj. Based on Figure 5b–e, and Table 2, it is evident that during the time interval from 3 ns to 3.04 ns, where C = 0, the logic inputs consist of (0, 0, 0), (0, 1, 0) and (0, 0, 1). In this scenario, APx = 8.74 · 10−5 < APy = 0.24, leading to the conclusion that O1 = 0 (as shown in Figure 5f,g); after a delay of τ (τ = 5 ns), specifically within the time interval from 8 ns to 8.04 ns, it is observed that ASx = 0.0078 < ASy = 0.92. Consequently, we conclude that O2 = 0 (as shown in Figure 5h,i). Therefore, it follows that . Between the time interval of 3.04 ns and 3.05 ns, the logic input corresponds to (1, 0, 0) with C = 1. Here, APx = 0.25 > APy = 5.83 · 10−4, resulting in O1 = 1. After a delay of τ, specifically within the time interval from 8.04 ns to 8.05 ns, it is observed that ASx = 0.56 > ASy = 0.35. Consequently, O2 = 1. Thus, we establish that . Between 3.05 ns and 3.06 ns, the logic input transitions to (1, 0, 1) with C = 0. Here, APx = 2.53 · 10−5 < APy = 0.25, leading to O1 = 0. Between 8.05 ns and 8.06 ns, it is observed that ASx = 0.31 < ASy = 0.75. Consequently, O2 = 0. Thus, we conclude that . The analysis principle for logic operations in other time intervals follows the same methodology; hence, it is not reiterated here. Based on the aforementioned analysis, it is concluded that . This signifies the successful implementation of data selection logic operations and their delay storage.
It is crucial to acknowledge that the fidelity of logic outputs is influenced by various system parameters, such as the bit duration time T and the noise strength Noi. These factors can introduce bit errors, potentially compromising the integrity of logic operations. Therefore, the success probability (SP) is employed as a metric to quantify the reliability of data selection logic operations. The SP is calculated as the ratio of the number of correctly identified symbols to the total number of symbols present in the output of the logic operations. The evolution of success probability (SP) for the logic outputs O1 and O2 is analyzed across the parameter space defined by noise strength Noi and bit duration time T, as depicted in Figure 6. Figure 6a illustrates that for Noi values below 185 dBw, the SP of O1 consistently remains at unity across a T range of 0.25 ps to 50 ps. Beyond 185 dBw, the SP of O1 falls below unity; however, its anti-noise performance can be significantly improved by increasing T. Figure 6b reveals that for T values below 8.75 ps, the SP of O2 is less than unity. In the scenario where Noi is less than 180 dBw and T exceeds 8.75 ps, the SP of O2 consistently achieves unity. Nevertheless, as Noi surpasses 180 dBw, the SP of O2 exhibits a gradual decline. From the analysis presented, it can be inferred that to ensure error-free operation for both O1 and O2, the bit duration time T must be set to at least 8.75 ps, and the noise strength Noi should be maintained below 180 dBw. This configuration suggests that the maximum operational speed for optical chaotic data selection is approximately 114 Gb/s. Furthermore, the superior anti-noise performance of O1 compared to O2 is attributed primarily to the more pronounced mutual suppression observed between xP-PC and yP-PC as opposed to that between xS-PC and yS-PC, which is illustrated in Figure 5f–i.
In summary, it is evident that when the bit duration time T exceeds 8.75 ps and the noise strength Noi falls within the range of 180 dBw to 185 dBw, the logic output O2 may encounter errors, whereas O1 remains error-free. Consequently, by comparing O2 with O1, it is feasible to detect erroneous symbols within O2 and subsequently implement error correction procedures. In this section, we exemplify the system’s error detection and correction capabilities by examining noise strengths of 179 dBw, 185 dBw and 190 dBw. The remaining system parameters are consistent with those depicted in Figure 5. At a noise strength of 179 dBw, Figure 7a illustrates that the noise exerts a pronounced effect on the amplitudes of xP-PC, yP-PC, xS-PC and yS-PC. Nonetheless, leveraging the superior mean comparison demodulation mechanism, the logic outputs O1 and O2 exhibit no errors. At a noise strength of 185 dBw, Figure 7b indicates that the logic output O1 remains error-free. Consequently, by comparing it with O1, it is observed that the logic output O2 incurs errors within the time frame of 8.11 ps to 8.16 ps. These errors are indicated with a black solid line and marked with the symbol ‘x’. The corrected logic outputs are depicted by a pink dotted line. When the noise strength is elevated to 190 dBw, as shown in Figure 7c, the logic output O1 encounters errors within the interval of 3.18 ps to 3.19 ps. Similarly, logic output O2 experiences errors in two distinct intervals: 8.1 ps to 8.11 ps and 8.18 ps to 8.19 ps. Thus, under these conditions, both logic outputs are susceptible to errors, leading to the failure of the logic operations.
4. Conclusions
Based on the chaotic polarization system of optically injected cascaded VCSELs, we propose a scheme for implementing high-speed optical chaotic data selection logic operations with the performance of error detection and correction. It has been observed that the S-VCSEL can emit chaotic laser output within a broader parameter space encompassing an applied electric field and optical injection amplitude. When the applied electric field is set to 11 kV/mm or 25 kV/mm and the optical injection amplitude is around 4.4, the polarized light emitted by the PPLN exhibits strong correlation with that emitted by the S-VCSEL. Moreover, both the PPLN and S-VCSEL demonstrate identical polarization bistability characteristics: under an applied electric field of 11 kV/mm, x-PC predominates, while y-PC is suppressed. Additionally, y-PC is entirely suppressed by x-PC when the optical injection amplitude exceeds 4.7. Under an applied electric field of 25 kV/mm, the predominant polarization is y-PC, with x-PC being suppressed. Similarly, when the optical injection amplitude exceeds 4.7, x-PC is completely suppressed by y-PC. Based on the aforementioned findings, we utilize the modulation of optical injection amplitude and an applied electric field as the logic input and control logic signal, respectively. Utilizing the outstanding mean comparison mechanism, we achieve two identical logic outputs through demodulating the polarized light from the PPLN and S-VCSEL. This enables the realization of high-speed optical chaotic data selection logic operations, achieving operational speeds of up to approximately 114 Gb/s. Through an examination of noise effects on the logic outputs, it was observed that neither logic output displayed any error symbols even under a noise strength as high as 180 dBw. Furthermore, the anti-noise performance of logic output O1 was found to be superior to that of optical chaotic logic output O2. Error symbols in O2 can be detected and corrected by comparison with O1 when the noise strength does not exceed 185 dBw.
Conceptualization, G.X. and K.W.; methodology, G.X. and K.W.; software, G.X. and K.W.; formal analysis, K.W., L.X. and J.D.; writing—original draft preparation, K.W.; writing—review and editing, G.X.; visualization, K.W. All authors have read and agreed to the published version of the manuscript.
Not applicable.
Not applicable.
Data are contained within the article.
The authors declare no conflicts of interest.
Footnotes
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Figure 1. Schematic diagram of high-speed optical chaotic data selection logic operations.
Figure 2. Evolutions of dynamic state of xS-PC and yS-PC in parameter space of EA and Einj. (a) xS-PC. (b) yS-PC.
Figure 3. The influence of the optical injection amplitude Einj on the correlation coefficient ρx,y under different applied electric fields. (a) EA = 11 kV/mm. (b) EA = 25 kV/mm.
Figure 4. The evolutions of the polarization bistability of xP-PC, yP-PC, xS-PC and yS-PC under different applied electric fields EA. (a) The polarization bistability of xP-PC and yP-PC under EA = 11 kV/mm. (b) The polarization bistability of xS-PC and yS-PC under EA = 11 kV/mm. (c) The polarization bistability of xP-PC and yP-PC under EA = 25 kV/mm. (d) The polarization bistability of xS-PC and yS-PC under EA = 25 kV/mm.
Figure 5. The optical chaotic data selection logic operations. (a) The combination of EA and Einj. (b) The control logic signal C. (c) The logic input I1. (d) The logic input I2. (e) The optical clock signal I3. (f) The combination of EPx and O1. (g) The combination of EPy and O1. (h) The combination of ESx and O2. (i) The combination of ESy and O2.
Figure 6. The evolutions of SP in the parameter space of Noi and T. (a) The SP of logic output O1. (b) The SP of logic output O2.
Figure 7. The influence of noise strength on logic output O1 and O2. (a) Noi = 179 dBw; (b) Noi = 185 dBw; (c) Noi = 190 dBw.
The main system parameters.
Parameters | Value | Parameters | Value |
---|---|---|---|
Linewidth enhancement factor a | 3 | Noise strength Noi | 100 dBw |
Field decay rate k | 300 ns−1 | Polar angle θ | π/2 |
Spin relaxation rate γs | 50 ns−1 | Azimuth φ | π/2 |
Nonradiative carrier relaxation γe | 1 ns−1 | Crystal temperature F | 293 K |
Dichroism γa | 2 ns−1 | Poled period of crystal Λ | 5.8 × 105 m−1 |
Birefringence γp | 60 ns−1 | Duty ratio D | 0.5 |
Delay time τ | 5 ns | Crystal length L | 15 mm |
Effective area of light spot SA | 7.0686 μm2 | Refractive index of o-light n1 | 2.24 |
Length of laser cavity Lv | 3 μm | Refractive index of e-light n2 | 2.17 |
Effective refractive index of active layer ng | 3.6 | Frequency detuning Δωs | 0 GHz |
Volume of active layer V | 21.206 μm3 | Frequency detuning Δω | 150 GHz |
Normalized bias current μM = μS | 1.2 | Wavelength of VCSEL λ | 1550 nm |
Optical injection strength kx = ky | 10 ns−1 | Optical injection strength kinjx = kinjy | 500 ns−1 |
Threshold current of VCSEL Ith | 6.8 mA | Bit duration time T | 10 ps |
The numerical values of APx, APy, ASx and ASy in different time periods.
Time (ns) | A Px | A Py | Time (ns) | A Sx | A Sy |
---|---|---|---|---|---|
3–3.04 | 8.74 · 10−5 | 0.24 | 8–8.04 | 0.0078 | 0.92 |
3.04–3.05 | 0.25 | 5.83 · 10−4 | 8.04–8.05 | 0.56 | 0.35 |
3.05–3.06 | 2.53 · 10−5 | 0.25 | 8.05–8.06 | 0.31 | 0.75 |
3.06–3.1 | 0.25 | 5.64 · 10−4 | 8.06–8.1 | 0.5 | 0.19 |
3.1–3.11 | 4.01 · 10−5 | 0.24 | 8.1–8.11 | 0.19 | 0.79 |
3.11–3.16 | 0.25 | 5.66 · 10−4 | 8.11–8.16 | 0.48 | 0.14 |
3.16–3.18 | 5.21 · 10−5 | 0.24 | 8.16–8.18 | 0.11 | 1 |
3.18–3.19 | 0.24 | 3.98 · 10−4 | 8.18–8.19 | 0.5 | 0.33 |
3.19–3.2 | 1.02 · 10−4 | 0.25 | 8.19–8.2 | 0.3 | 0.82 |
3.2–3.24 | 0.24 | 5.75 · 10−4 | 8.2–8.24 | 0.51 | 0.2 |
3.24–3.29 | 7.08 · 10−5 | 0.25 | 8.24–8.29 | 0.04 | 0.9 |
3.29–3.3 | 0.25 | 5.83 · 10−4 | 8.29–8.3 | 0.56 | 0.35 |
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Abstract
Based on the chaotic polarization system of optically injected cascaded vertical-cavity surface-emitting lasers (VCSELs), we propose a novel implementation scheme for high-speed optical chaotic data selection logic operations. Under the condition where the slave VCSEL (S-VCSEL) outputs a chaotic laser signal, we calculate the range of the applied electric field and the optical injection amplitude. We also investigate the evolution of the correlation characteristics between the polarized light output from the periodic poled LiNbO3 (PPLN) and the S-VCSEL as a function of the optical injection amplitude under different applied electric fields. Furthermore, we analyze the polarization bistability of the polarized light from the PPLN and S-VCSEL. Based on these results, we modulate the optical injection amplitude as the logic input and the applied electric field as the control logic signal. Using a mean comparison mechanism, we demodulate the polarized light from the PPLN and S-VCSEL to obtain two identical logic outputs, achieving optical chaotic data selection logic operations with an operation speed of approximately 114 Gb/s. Finally, we investigate the influence of noise on the logic outputs and find that both logic outputs do not show any error symbols under the noise strength as high as 180 dBw. The anti-noise performance of logic output O1 is superior to that of optical chaotic logic output O2. For noise strengths up to 185 dBw, error symbols in O2 can be detected and corrected by comparison with O1.
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1 School of Electronic Engineering, Chaohu University, Hefei 238024, China;
2 School of Computer Science and Artificial Intelligence, Chaohu University, Hefei 238024, China;