A Conclusive Algorithm with Kink Effects for Fitting 3-D FinFET and Planar MOSFET Characteristic Curves

Abstract

FinFET transistors with fin channel lengths of 160 nm and 2000 nm and a planar MOSFET transistor with channel lengths of 180 nm and 90 nm are presented with characteristic curves at various Gate biases. A finalized algorithm with kink effects was effectively responsible for addressing the field effect transistors. The algorithm included the modified conventional current–voltage formula and a nonlinear heat-associated kink solution which was simplified as a Gaussian form. Three parameters in the modified model included k_N (which was related with channel width, channel length, and gate oxide capacitor, and was proportional to the mobility of carriers), Vth (threshold voltage), and λ (the inverse of early voltage). Those parameters were determined to minimize the discrepancies between the measured data and the fitting values, but left kinks located at around (V_GS-Vth), which were deliberately eliminated by the Gaussian form because of the agitation of thermal kink effects. The whole fitting was made to be as close as possible to the as-measured I_DS-V_DS. In the meantime, those determined parameters were physically meaningful after the analysis had been performed.

1. Introduction

Transistors are the miniature of devices of automatic control that allow or disallow current to flow and convey signals or power. Power-discrete transistors concern a high breakdown voltage and a high current. Transistors that are responsible for signal communications continuously shrink for the requirement of faster speed. Unfortunately, continuous channel length shrinkage causes short channel effects. Short channel effects result in unwanted noticeable leakage current, which is successfully suppressed through a halo implant or a pocket implant on, e.g., planar MOSFET with a 0.18 μm or 90 nm long channel, in which the gate caps on the top of the channel. Unfortunately, the implant process fails to effectively stop leakage current at, e.g., 20 nm. Instead, FinFET sustains the capability of suppression of outrageously leaky current by using a Gate over 90% surrounding the 3-D slim channel for down to 3 nm process technique. GAAFET replaces the role of FinFET using the Gate completely surrounding the whole channel for 2 nm process technique. For one thing, the suppression of leakage current is due to creating a depletion region in thin epi-taxial silicon which blocks the leakage current by building up a hill high potential barrier. However, the trend of shorter channels promotes the speed of transmitting signals via carriers and makes artificial intelligence (AI) possible, where the non-linear problem-sorting deep neural network (DNN), image-sorting convolution neural network (CNN), and speech-recognizing recurrent neural network (RNN) become available [1,2,3,4,5,6].

Epi-silicon is tremendously important for its nearly identically flawless pure silicon that allows no enhancement of leakage current. Thicker epi-silicon films, such as tens of μm or a hundred μm, even play roles of power discrete with high sustainable voltage bias. Thinner epi-silicon, such as 10 μm, is expected on an integrated circuit (IC) though. Looking like an emerging 3-D “I” with two ends of source and drain, FinFET uses Gate poly-silicon crossing over the channel to conduct current between the source and the drain by applying a bias to the Gate. Simultaneously, the Gate bias depletes the whole slim channel and builds up a barrier that blocks the leakage current. The achievable function of the process is mostly due to the good conformality (step coverage) of chemical vapor deposition, in which SiH₄ (silane) is controlled at a chosen flow rate and the ambient is sustained at an appropriate temperature and at certain pressure to achieve a good deposition rate in the kinetic regime [7,8,9,10,11,12,13,14,15].

Somehow, the electrical performances of transistors are mainly manifested in current-versus-voltage characteristic curves. Those curves are necessarily parameter-extracted in the model, which is useful to develop the circuit design. Therefore, the as measured I–V curves are thought to be well fitted to determine predominant parameters. An advisable algorithm using the “modified” conventional I–V characteristic curve formula along with kink effects generates fitting data to minimize the deviations from the measured ones. The as-determined parameters are promising, such as the threshold voltage (Vth), lambda (λ), and k_N, which is mainly proportional to the mobility.

In this study, the fabrication of FinFET is roughly described and devices are randomly selected on the wafer level and measured as mentioned in Section 2.1. In Section 2.2, the two-regime modified formulas are proposed to fit current–voltage characteristic curves following the procedures or specific algorithm in Section 2.3. Results, including the determined parameters and fitting graphs mainly on I_DS-V_DS at various V_GS, are presented in Section 3, since I_DS-V_GS at various V_DS share the same formula. The results are analyzed and discussed in Section 4. As depicted in Section 5, several points are concluded.

2. Preparation, Measurements, and Fitting Algorithm

2.1. Preparation and Measurement of NFinFET

The grown 10 μm epi-silicon layer was ionic dry etched to form a 3-dimensional 120 nm wide and corresponding 9 times high fin channel. With two ends as Source and Drain, the whole epi-silicon channel looks like a letter “I”, which was followed with a grown thin gate oxide. The slim channel of “I” was then covered with arsenic heavily doped poly-silicon, called Gate. As the Gate is applied with a positive bias, the channel surrounded with Gate is then almost completely depleted, and right underneath the gate oxide, about 200 angstroms [16] p-type silicon is strongly inversed into effectively 90 nm long n-type silicon. The I_DS versus V_DS was then measured at various Gate biases on Agilent 4156C (Santa Clara, CA, USA).

2.2. Fitting I_DS-V_DS and I_DS-V_GS

The two-regime conventional formulas for FinFET and MOSFET transistors have to be modified as follows:

(1)$\begin{array}{ll}{I}_{DS}(triode)& =k_N[(V_{GS}-V_{th})V_{DS}-{\displaystyle \frac{V_{DS}^2}{2}}](1+\lambda V_{DS})\\ & -\alpha \exp [-\beta {({\mathrm{V}}_{\mathrm{DS}}-\chi )}^2]\end{array}$

and

(2)$$\begin{gathered} \begin{array}{ll}{I}_{DS}(saturation)=& k_N[{\displaystyle \frac{{(V_{GS}-V_{th})}^2}{2}}](1+\lambda V_{DS})\\ & -\alpha \exp [-\beta {({\mathrm{V}}_{\mathrm{DS}}-\chi )}^2]\end{array} \\ where k_N={\displaystyle \frac{{C_{ox}}^{(1)}{W}_{eff}\mu }{L_o}},\lambda ={\displaystyle \frac{1}{\left|V_A\right|}},and (\chi ,\alpha )\equiv (V_{DS\_kink},I_{DS\_kink}), \end{gathered}$$

where V_A is early voltage, C_ox⁽¹⁾ is gate oxide capacitance per square meter, L_o is channel length, μ is the mobility of carriers, and W_eff = 19W_o (W_o, fin width); and where β (V⁻²) is for the kink width adjustment [16,17,18,19,20,21]. Charge carriers travel through the strongly inversed layer with the speed variation in triode region which is proportional to the slopes of I_DS-V_DS. Charge carriers radiate electromagnetic wave, called Bremsstruhlung, with the speed of forward light at 2.997 × 10⁸/11.9 m/s, intensively heat up the lattice in advance, and definitely cause the extra vibration of the lattice ahead of carriers (quantized as phonons). The corresponding current corrections (due to heat vibration of lattice) ensure the reduction of I_DS as presented in Figure 1, Figure 2, Figure 3 and Figure 4. The subtraction of current–voltage data of substitutions in Equations (1) and (2) from the as-measured data is named ΔI_DS, which is always positive in triode region forming a Gaussian-like peak at (χ,α) with a β-controlled width as drawn in Figure 2b and Figure 3b. In order to achieve kink effect adjustment, those peaks are expected to be eliminated as δ-deviations are minimized.

Equation (1) or Equation (2) work as V_DS is less than or larger than (V_GS-Vth), respectively. And those parameters (k_N, Vth, λ, α, β, χ) are deliberately determined to minimize the delta (δ) in Equation (3) as follows:

(3)$\delta =\sqrt{{\displaystyle \frac{{\displaystyle \sum _{i=1}^N{{(I_{fitting}-I_{measured})}_i}^2}}{N}}}$

2.3. Fitting Algoritm

First, the minimum delta (δ) in Equation (3) may be used to first determine lambda (λ) by adjusting k_N and Vth, leaving the locations of kinks at around V_DS = (V_GS − Vth). Secondly, the discrepancies between the measured data and the fitting data are found to determine (χ, α) in Equations (1) and (2). Finally, the width of the kink (associated with β) at different V_GS is to be determined using Equation (3). In total, six parameters, (k_N, Vth, λ, α, β, χ)_VG are used to fit a specific characteristic curve well [21]. Different sets of six parameters at various values of V_G may be applied as beams to determine the different characteristic curves at other different gate bias. Once the fitting for I_DS-V_DS is as perfect as possible, the whole electrical performance can be addressed because even I_DS-V_GS is also expressed in the same formula.

3. Results

There are four transistors presented in this study, including two FinFET W120L160 and W120L2000 transistors (Manufactured in National Chip Implementation Center, Hsinchu city, Taiwan, fin width = 120 nm, channel length = 160 nm, 2000 nm), and two planar MOSFET L180 nm and L90 nm transistors (TSMC, Hsinchu city, Taiwan, channel length = 180 nm, 90 nm). According to the algorithm as described in Section 2.3, the measured data were deliberately fitted with a conventional model formula with a significant modification like that shown in Equations (1) and (2). Parameters at various Gate biases were then determined for fitting the as-measured characteristic curves and these are listed in Table 1, Table 2, Table 3 and Table 4.

As shown in Figure 1 (FinFET W120L160), Figure 2 (FinFET W120L2000), Figure 3 (planar MOSFET L180), and Figure 4 (planar MOSFET L90), the fittings with and without kink (heat or phonon effects) adjustment are presented in (a) and (c), respectively. The subtractions of the fitting data from the as-measured data with and without kink (heat or phonon effects) adjustment are thus found in (b) and (d), respectively. It is interesting to notice that (b) provides extra information about the geometrical designs of the transistors. For FinFET with double Gate side effects, mono-peaks or two-peaks occur in Figure 1b and Figure 2b, while only monopoles are found in planar MOSFET, as shown in Figure 3b and Figure 4b. Kinks were set to the peak coordinates (χ, α)_peak, where χ is the V_DS value of the peak (such as in Figure 3b) or somewhere between the twin peaks (such as in Figure 2b). The parameters (χ, α) were determined by observing the peaks. The beta (β) was varied to find the minimum δ deviation depending on the peak width and this resulted in (c), (d), and (e) in Figure 1, Figure 2, Figure 3 and Figure 4. Actually, carriers received thermal agitations from the kinks, which may cause lower I_DS current flow. For the planar MOSFETs in Table 3 and Table 4 without double Gate side effects, β was smaller as the applied gate bias, V_GS, was larger. With double Gate side effects in Table 1 and Table 2, no regulation was found.

4. Analysis and Discussion

The three main parameters listed in Table 1, Table 2, Table 3 and Table 4 are associated with certain physical meanings. It is interesting to see the linearly dependent association as shown in Figure 5 such that the kink and (V_GS-Vth) are strongly correlated and linearly dependent to each other as well. This demonstrates and enhances the idea of the kink effects addressing the phonon disturbances on, scattering from, and coupling with the carriers degrading the electrical performances.

Furthermore, k_N, with geometrical fixed sizes, was proportional to mobility (μ), which is demonstrated as a constant value at fixed V_GS. However, at different applied V_GS bias, mobility was definitely varied and proportional to (V_GS-Vth)^−1/3, as shown in Figure 6a,b. That is due to the stronger (V_GS-Vth) field attracting more carriers closer to the interface between the gate oxide and the strongly inversed silicon layer where carriers move, confronting more obstacles. As for the power of (−1/3), there shall be a mechanism that provides the association between the speed of carrier and the source–drain field, which is perpendicularly influenced from the gate side.

Moreover, the threshold voltages (Vth) varied at various V_GS not only for FinFET but also for MOSFET, where V_tho may be written as follows:

(4)$\begin{array}{l}{V}_{tho}={(-0.56-\left|{\mathsf{\Phi }}_p\right|)}_{FB}-{\displaystyle \frac{Q_{ox}^{\prime }}{C_{ox}^{\prime }}}+2\left|{\mathsf{\Phi }}_p\right|+{\displaystyle \frac{Q_{dep}^{\prime }}{C_{ox}^{\prime }}}\\ with\\ \left|{\mathsf{\Phi }}_p\right|={\displaystyle \frac{kT}{e}}\ln ({\displaystyle \frac{p}{n_i}}),\\ and\\ Q_{dep}=peD=\sqrt{2{\epsilon }_{Si}pe\left|2{\mathsf{\Phi }}_p\right|}\end{array}$

where “FB” means flat-band voltage, Q_ox is the charge located in the oxide layer, C_ox’ is the unit capacitance, and Q_dep is the space charge in the depletion region. Also, p is defined to be the concentration in p-type semiconductor, and D means the thickness of the depletion region. V_GS = 2|Φ| is the basic applied voltage that causes the strongly inversed layer for V_tho. V_tho is called the zero-order threshold voltage and is thought to be the minimum Gate bias which enables the Fermi energy to be lower than the intrinsic Fermi energy and simultaneously sustain the space charge in the induced depletion region. Somehow, Equation (4) is rewritten as the following fitting formula:

(5)$\begin{array}{l}{V}_{th}=-0.56-{\displaystyle \frac{Q_{ox}^{\prime }}{C_{ox}^{\prime }}}+\left|{\mathsf{\Phi }}_p\right|+{\displaystyle \frac{\sqrt{2{\epsilon }_{Si}pe\left|2{\mathsf{\Phi }}_p\right|}}{C_{ox}^{\prime }}}\\ V_{th}\stackrel{\mathsf{\Phi }\to {\mathsf{\Phi }}_o+{\alpha }_{eff}{V}_{GS}}{\to }{V}_{tho}+{\alpha }_{eff}f(V_{GS})+{\beta }_{eff}\sqrt{f(V_{GS})}\\ with\\ \left|{\beta }_{eff}\right|={\displaystyle \frac{\sqrt{4{\epsilon }_{Si}pe}}{C{\prime }_{OX}}},\\ and\\ f(V_{GS})\stackrel{empirically}{\to }=\left\{\begin{array}{l}1-V_{GS},(FinFET)\\ V_{GS},(MOSFET)\end{array}\right.\end{array}$

$\begin{array}{l}where\\ C{\prime }_{OX\_FinFET}=({\displaystyle \frac{{\epsilon }_{OX}}{24\times {10}^{-10}}})=({\displaystyle \frac{3.9\times 8.85\times {10}^{-12}}{24\times {10}^{-10}}}),\\ C{\prime }_{OX\_MOSFET}=({\displaystyle \frac{{\epsilon }_{OX}}{60\times {10}^{-10}}})=({\displaystyle \frac{5.2\times 8.85\times {10}^{-12}}{60\times {10}^{-10}}}),\\ and\\ {\epsilon }_{Si}=11.9{\epsilon }_o=11.9\times 8.85\times {10}^{-12}F/m\end{array}$

In Equation (5), α_eff (effective screening parameter) and β_eff are the slopes of f(V_GS) and [f(V_GS)]^1/2, respectively. Also for FinFET, f(V_GS) = (1 − V_GS) was deliberately set to the fixed condition of V_GS at 1.0 V, where the threshold voltage was set to −0.007 V, as in Table 2. Also, f(V_GS) = V_GS was deliberately set to the fixed condition of V_GS at 1.5 V, where the threshold voltage was set to 0.931 V, as in Table 3 [22]. In the fitting presented in Figure 7a,b, |β_eff| = 0.085 and |β_eff| = 0.1 correspond to p = 4.4 × 10²³ (1/m³) and p = 1.6163 × 10²² (1/m³), which help to identify the thickness of the strongly inversed layer to be 182 angstrom at V_{GS_FinFET} = 1.0 V and 92 angstrom at V_{GS_MOSFET} = 0.4 V, as shown in Figure 7c.

As presented in Figure 8, λ(|V_A⁻¹|) signifies the leakage current slope across the source and the drain, and shows suppression as (V_GS − Vth) increases, which means that a more depleted region induces a leakage current reduction. All transistors are usually leakier if (V_GS − Vth) is small because of the smaller depleted region. Somehow, FinFET_L2000 has more leakage current because the thickness of the gate oxide is designed to be around 20 Å. Also, MOSFET_L90 has less leakage current owing to the halo implant or pocket implant taking effect.

Furthermore, without kink effect adjustments, the fitting parameters for W120L2000 are presented in Table 5. In addition, three FinFET transistors, such as W120L100, W120L160, and W120L240, are also taken into account [16]. As noted, k_N value is inversely proportional to the channel length and this is plotted in Figure 9, which is verified to be linear as expected.

5. Conclusions

The modified characteristic formulas in Equations (1) and (2) with kink effects (phonon disturbances) are provided to fit the as-measured current–voltage curves. The kinks are always located at the joint of the triode region and the saturation region. The authors noticed many conclusive points, presented as follows: (1) Three parameters (k_N, Vth, λ) were determined and found to be different at different V_GS. (2) δ deviation helps improve the fitting to be as complete as possible, and may help distinguish a FinFET structure from a planar MOSFET one, as shown in Figure 1b, Figure 2b, Figure 3b and Figure 4b. (3) The mobility at certain fixed Gate voltages, which is proportional to k_N, was constant but varied at various Gate biases. For FinFET and MOSFET in Figure 6, k_N was found to be almost linearly dependent on (V_GS-Vth)^−1/3, and so was mobility. (4) The determined Vth was found to be V_GS-dependent too. An empirical equation, which takes advantage of the definition of V_tho, is proposed in order to find β and thus the concentration (p) of doped boron, which may be used to calculate the thickness of the strong inversion layer in Figure 7. (5) In Figure 8, the early voltage-associated λ (|V_A⁻¹|), which is inversely linearly dependent of (V_GS-Vth), becomes flatter as (V_GS-Vth) becomes larger. This indicates that a higher field results in more depletion of the substrate which depresses the leakage current. (6) k_N was inversely proportional to the channel length, as verified in Figure 9 at a specific gate bias, e.g., V_GS = 1.00 V.

Author Contributions

Conceptualization, H.-C.Y. and S.-C.C.; methodology, H.-C.Y., S.-C.C., H.-Y.Y. and Y.-T.Y.; software, H.-C.Y. and S.-C.C.; validation, H.-C.Y. and S.-C.C.; formal analysis, H.-C.Y. and S.-C.C.; investigation, H.-C.Y. and S.-C.C.; resources, H.-C.Y. and S.-C.C.; data duration, H.-C.Y. and S.-C.C. All authors have read and agreed to the published version of the manuscript.

Institutional Review Board Statement

Not available.

Informed Consent Statement

Not available.

Data Availability Statement

The raw data supporting the conclusions of this article will be made available by the authors on request.

Conflicts of Interest

The authors declare no conflicts of interest.

Footnotes

Disclaimer/Publisher’s Note: The statements, opinions and data contained in all publications are solely those of the individual author(s) and contributor(s) and not of MDPI and/or the editor(s). MDPI and/or the editor(s) disclaim responsibility for any injury to people or property resulting from any ideas, methods, instructions or products referred to in the content.

Figures and Tables

Figure 1. (a) FinFET fitting without kink effect adjustment on thermal phonon collisions. (b) Minimum deviation without kink effect adjustment: δ = 1.17 × 10−6 A (at VGS = 1.0 V), δ = 9.77 × 10−7 A (at VGS = 0.75 V), δ = 9.60 × 10−7 A (at VGS = 0.5 V), and δ = 1.51 × 10−7 A (at VGS = 0.25 V). (c) FinFET fitting with kink effect adjustment on thermal phonon collisions. (d) Minimum deviation with kink effect adjustment: δ = 2.58 × 10−7 A (at VGS = 1.0 V), δ = 1.77 × 10−7 A (at VGS = 0.75 V), δ = 2.01 × 10−7 A (at VGS = 0.5 V), and δ = 4.08 × 10−8 A (at VGS = 0.25 V). (e) Finalizing minimum deviation by adjusting β: δ = 2.58 × 10−7 A (at VGS = 1.0 V).

Figure 1. (a) FinFET fitting without kink effect adjustment on thermal phonon collisions. (b) Minimum deviation without kink effect adjustment: δ = 1.17 × 10−6 A (at VGS = 1.0 V), δ = 9.77 × 10−7 A (at VGS = 0.75 V), δ = 9.60 × 10−7 A (at VGS = 0.5 V), and δ = 1.51 × 10−7 A (at VGS = 0.25 V). (c) FinFET fitting with kink effect adjustment on thermal phonon collisions. (d) Minimum deviation with kink effect adjustment: δ = 2.58 × 10−7 A (at VGS = 1.0 V), δ = 1.77 × 10−7 A (at VGS = 0.75 V), δ = 2.01 × 10−7 A (at VGS = 0.5 V), and δ = 4.08 × 10−8 A (at VGS = 0.25 V). (e) Finalizing minimum deviation by adjusting β: δ = 2.58 × 10−7 A (at VGS = 1.0 V).

Figure 1. (a) FinFET fitting without kink effect adjustment on thermal phonon collisions. (b) Minimum deviation without kink effect adjustment: δ = 1.17 × 10−6 A (at VGS = 1.0 V), δ = 9.77 × 10−7 A (at VGS = 0.75 V), δ = 9.60 × 10−7 A (at VGS = 0.5 V), and δ = 1.51 × 10−7 A (at VGS = 0.25 V). (c) FinFET fitting with kink effect adjustment on thermal phonon collisions. (d) Minimum deviation with kink effect adjustment: δ = 2.58 × 10−7 A (at VGS = 1.0 V), δ = 1.77 × 10−7 A (at VGS = 0.75 V), δ = 2.01 × 10−7 A (at VGS = 0.5 V), and δ = 4.08 × 10−8 A (at VGS = 0.25 V). (e) Finalizing minimum deviation by adjusting β: δ = 2.58 × 10−7 A (at VGS = 1.0 V).

Figure 2. (a) FinFET fitting without kink effect adjustment on thermal phonon collisions. (b) Minimum deviation without kink effect adjustment: δ = 7.63 × 10−7 A (at VGS = 1.0 V), δ = 6.89 × 10−7 A (at VGS = 0.75 V), δ = 5.33 × 10−7 A (at VGS = 0.5 V), and δ = 2.29 × 10−7 A (at VGS = 0.25 V). (c) FinFET fitting with kink effect adjustment on thermal phonon collisions. (d) Minimum deviation with kink effect adjustment: δ = 1.23 × 10−7 A (at VGS = 1.0 V), δ = 1.19 × 10−7 A (at VGS = 0.75 V), δ = 9.26 × 10−8 A (at VGS = 0.5 V), and δ = 3.46 × 10−8 A (at VGS = 0.25 V). (e) Finalizing minimum deviation by adjusting β: δ = 1.23 × 10−7 A (at VGS = 1.0 V)

Figure 2. (a) FinFET fitting without kink effect adjustment on thermal phonon collisions. (b) Minimum deviation without kink effect adjustment: δ = 7.63 × 10−7 A (at VGS = 1.0 V), δ = 6.89 × 10−7 A (at VGS = 0.75 V), δ = 5.33 × 10−7 A (at VGS = 0.5 V), and δ = 2.29 × 10−7 A (at VGS = 0.25 V). (c) FinFET fitting with kink effect adjustment on thermal phonon collisions. (d) Minimum deviation with kink effect adjustment: δ = 1.23 × 10−7 A (at VGS = 1.0 V), δ = 1.19 × 10−7 A (at VGS = 0.75 V), δ = 9.26 × 10−8 A (at VGS = 0.5 V), and δ = 3.46 × 10−8 A (at VGS = 0.25 V). (e) Finalizing minimum deviation by adjusting β: δ = 1.23 × 10−7 A (at VGS = 1.0 V)

Figure 2. (a) FinFET fitting without kink effect adjustment on thermal phonon collisions. (b) Minimum deviation without kink effect adjustment: δ = 7.63 × 10−7 A (at VGS = 1.0 V), δ = 6.89 × 10−7 A (at VGS = 0.75 V), δ = 5.33 × 10−7 A (at VGS = 0.5 V), and δ = 2.29 × 10−7 A (at VGS = 0.25 V). (c) FinFET fitting with kink effect adjustment on thermal phonon collisions. (d) Minimum deviation with kink effect adjustment: δ = 1.23 × 10−7 A (at VGS = 1.0 V), δ = 1.19 × 10−7 A (at VGS = 0.75 V), δ = 9.26 × 10−8 A (at VGS = 0.5 V), and δ = 3.46 × 10−8 A (at VGS = 0.25 V). (e) Finalizing minimum deviation by adjusting β: δ = 1.23 × 10−7 A (at VGS = 1.0 V)

Figure 3. (a) L180-MOSFET fitting without kink effect adjustment on thermal phonon collisions. (b) Minimum deviation without kink effect adjustment: δ = 1.92 × 10−3 A (at VGS = 2.5 V), δ = 1.27 × 10−3 A (at VGS = 2.2 V), δ = 1.24 × 10−3 A (at VGS = 2.0 V), and δ = 9.40 × 10−4 A (at VGS = 1.8 V), δ = 8.56 × 10−4 A (at VGS = 1.5 V), δ = 6.09 × 10−4 A (at VGS = 1.2 V), δ = 4.08 × 10−4 A (at VGS = 1.0 V), and δ = 2.27 × 10−4 A (at VGS = 0.8 V). (c) L180-MOSFET fitting with kink effect adjustment on thermal phonon collisions. (d) Minimum deviation with kink effect adjustment: δ = 3.03 × 10−4 A (at VGS = 2.5 V), δ = 2.00 × 10−4 A (at VGS = 2.2 V), δ = 2.77 × 10−4 A (at VGS = 2.0 V), δ = 1.91 × 10−4 A (at VGS = 1.8 V), δ = 1.46 × 10−3 A (at VGS = 1.5 V), δ = 1.40 × 10−4 A (at VGS = 1.2 V), δ = 7.82 × 10−5 A (at VGS = 1.0 V), and δ = 6.81 × 10−5 A (at VGS = 0.8 V). (e) Finalizing minimum deviation by adjusting β: δ = 3.03 × 10−4 A (at VGS = 2.5 V).

Figure 3. (a) L180-MOSFET fitting without kink effect adjustment on thermal phonon collisions. (b) Minimum deviation without kink effect adjustment: δ = 1.92 × 10−3 A (at VGS = 2.5 V), δ = 1.27 × 10−3 A (at VGS = 2.2 V), δ = 1.24 × 10−3 A (at VGS = 2.0 V), and δ = 9.40 × 10−4 A (at VGS = 1.8 V), δ = 8.56 × 10−4 A (at VGS = 1.5 V), δ = 6.09 × 10−4 A (at VGS = 1.2 V), δ = 4.08 × 10−4 A (at VGS = 1.0 V), and δ = 2.27 × 10−4 A (at VGS = 0.8 V). (c) L180-MOSFET fitting with kink effect adjustment on thermal phonon collisions. (d) Minimum deviation with kink effect adjustment: δ = 3.03 × 10−4 A (at VGS = 2.5 V), δ = 2.00 × 10−4 A (at VGS = 2.2 V), δ = 2.77 × 10−4 A (at VGS = 2.0 V), δ = 1.91 × 10−4 A (at VGS = 1.8 V), δ = 1.46 × 10−3 A (at VGS = 1.5 V), δ = 1.40 × 10−4 A (at VGS = 1.2 V), δ = 7.82 × 10−5 A (at VGS = 1.0 V), and δ = 6.81 × 10−5 A (at VGS = 0.8 V). (e) Finalizing minimum deviation by adjusting β: δ = 3.03 × 10−4 A (at VGS = 2.5 V).

Figure 3. (a) L180-MOSFET fitting without kink effect adjustment on thermal phonon collisions. (b) Minimum deviation without kink effect adjustment: δ = 1.92 × 10−3 A (at VGS = 2.5 V), δ = 1.27 × 10−3 A (at VGS = 2.2 V), δ = 1.24 × 10−3 A (at VGS = 2.0 V), and δ = 9.40 × 10−4 A (at VGS = 1.8 V), δ = 8.56 × 10−4 A (at VGS = 1.5 V), δ = 6.09 × 10−4 A (at VGS = 1.2 V), δ = 4.08 × 10−4 A (at VGS = 1.0 V), and δ = 2.27 × 10−4 A (at VGS = 0.8 V). (c) L180-MOSFET fitting with kink effect adjustment on thermal phonon collisions. (d) Minimum deviation with kink effect adjustment: δ = 3.03 × 10−4 A (at VGS = 2.5 V), δ = 2.00 × 10−4 A (at VGS = 2.2 V), δ = 2.77 × 10−4 A (at VGS = 2.0 V), δ = 1.91 × 10−4 A (at VGS = 1.8 V), δ = 1.46 × 10−3 A (at VGS = 1.5 V), δ = 1.40 × 10−4 A (at VGS = 1.2 V), δ = 7.82 × 10−5 A (at VGS = 1.0 V), and δ = 6.81 × 10−5 A (at VGS = 0.8 V). (e) Finalizing minimum deviation by adjusting β: δ = 3.03 × 10−4 A (at VGS = 2.5 V).

Figure 4. (a) L90-MOSFET fitting without kink effect adjustment on thermal phonon collisions. (b) Minimum deviation without kink effect adjustment: δ = 7.35 × 10−6 A (at VGS = 2.2 V), δ = 5.05 × 10−6 A (at VGS = 2.0 V), δ = 3.29 × 10−6 A (at VGS = 1.8 V), δ = 2.15 × 10−6 A (at VGS = 1.5 V), δ = 1.35 × 10−6 A (at VGS = 1.2 V), δ = 1.02 × 10−6 A (at VGS = 1.0 V), and δ = 6.97 × 10−7 A (at VGS = 0.8 V). (c) L90-MOSFET fitting with kink effect adjustment on thermal phonon collisions. (d) Minimum deviation with kink effect adjustment: δ = 1.35 × 10−6 A (at VGS = 2.2 V), δ = 1.29 × 10−6 A (VGS = 2.0 V), δ = 1.15 × 10−6 A (at VGS = 1.8 V), δ = 3.17 × 10−7 A (at VGS = 1.5 V), δ = 2.17 × 10−7 A (at VGS = 1.2 V), δ = 1.61 × 10−7 A (at VGS = 1.0 V), and δ = 1.68 × 10−7 A (at VGS = 0.8 V). (e) Finalizing minimum deviation by adjusting β: δ = 1.35 × 10−6 A (VGS = 2.2 V).

Figure 4. (a) L90-MOSFET fitting without kink effect adjustment on thermal phonon collisions. (b) Minimum deviation without kink effect adjustment: δ = 7.35 × 10−6 A (at VGS = 2.2 V), δ = 5.05 × 10−6 A (at VGS = 2.0 V), δ = 3.29 × 10−6 A (at VGS = 1.8 V), δ = 2.15 × 10−6 A (at VGS = 1.5 V), δ = 1.35 × 10−6 A (at VGS = 1.2 V), δ = 1.02 × 10−6 A (at VGS = 1.0 V), and δ = 6.97 × 10−7 A (at VGS = 0.8 V). (c) L90-MOSFET fitting with kink effect adjustment on thermal phonon collisions. (d) Minimum deviation with kink effect adjustment: δ = 1.35 × 10−6 A (at VGS = 2.2 V), δ = 1.29 × 10−6 A (VGS = 2.0 V), δ = 1.15 × 10−6 A (at VGS = 1.8 V), δ = 3.17 × 10−7 A (at VGS = 1.5 V), δ = 2.17 × 10−7 A (at VGS = 1.2 V), δ = 1.61 × 10−7 A (at VGS = 1.0 V), and δ = 1.68 × 10−7 A (at VGS = 0.8 V). (e) Finalizing minimum deviation by adjusting β: δ = 1.35 × 10−6 A (VGS = 2.2 V).

Figure 4. (a) L90-MOSFET fitting without kink effect adjustment on thermal phonon collisions. (b) Minimum deviation without kink effect adjustment: δ = 7.35 × 10−6 A (at VGS = 2.2 V), δ = 5.05 × 10−6 A (at VGS = 2.0 V), δ = 3.29 × 10−6 A (at VGS = 1.8 V), δ = 2.15 × 10−6 A (at VGS = 1.5 V), δ = 1.35 × 10−6 A (at VGS = 1.2 V), δ = 1.02 × 10−6 A (at VGS = 1.0 V), and δ = 6.97 × 10−7 A (at VGS = 0.8 V). (c) L90-MOSFET fitting with kink effect adjustment on thermal phonon collisions. (d) Minimum deviation with kink effect adjustment: δ = 1.35 × 10−6 A (at VGS = 2.2 V), δ = 1.29 × 10−6 A (VGS = 2.0 V), δ = 1.15 × 10−6 A (at VGS = 1.8 V), δ = 3.17 × 10−7 A (at VGS = 1.5 V), δ = 2.17 × 10−7 A (at VGS = 1.2 V), δ = 1.61 × 10−7 A (at VGS = 1.0 V), and δ = 1.68 × 10−7 A (at VGS = 0.8 V). (e) Finalizing minimum deviation by adjusting β: δ = 1.35 × 10−6 A (VGS = 2.2 V).

Figure 5. (VGS-Vth) versus VGS, and versus VGS. (a) FinFET W120L90, (b) MOSFET L180, (c) MOS FET L090.

Figure 5. (VGS-Vth) versus VGS, and versus VGS. (a) FinFET W120L90, (b) MOSFET L180, (c) MOS FET L090.

Figure 6. (a) kN is proportional to (VGS-Vth)−1/3 for MOSFET_L180; (b) kN is proportional to (VGS-Vth)−1/3 for FinFET_L160, FinFET_L2000, and MOSFET_L-90. The kN’ shown is for MOSFET_L180, whose channel width is divided by 750.

Figure 6. (a) kN is proportional to (VGS-Vth)−1/3 for MOSFET_L180; (b) kN is proportional to (VGS-Vth)−1/3 for FinFET_L160, FinFET_L2000, and MOSFET_L-90. The kN’ shown is for MOSFET_L180, whose channel width is divided by 750.

Figure 7. (a) Vth versus VGS for FinFET, (b) Vth versus VGS for FinFET, and (c) depletion region and strongly inversed layer in energy region presentation.

Figure 8. λ versus (VGS−Vth)−1 for FinFET_L2000, MOSFET_L180, and MOSFET_L90 MOSFET.

Figure 9. kN for four FinFET transistors is linearly dependent of the inverse of channel length.

Table 1

Determined parameters of FinFET W120L160 (fin Width = 120 nm, Length = 160 nm), where δ = 2.58 × 10⁻⁷ A with kink modification and δ = 1.17 × 10⁻⁶ A without kink modification at V_GS = 1.00 V.

Gate Bias	kN (A/V2)	Vth (V)	λ	α (A)	β (V−2)	χ (V)
VGS = 0.25 V	1.71 × 10−4	−0.140	0.105	4.60 × 10−7	105.0	0.34
VGS = 0.50 V	1.66 × 10−4	−0.165	0.080	1.40 × 10−6	7.0	0.36
VGS = 0.75 V	1.46 × 10−4	−0.132	0.163	1.88 × 10−6	16.0	0.25
VGS = 1.00 V	1.29 × 10−4	−0.101	0.154	2.24 × 10−6	19.0	0.29

Table 2

Determined parameters of FinFET W120L2000 (fin Width = 120 nm, Length = 2000 nm), where δ = 1.23 × 10⁻⁷ A with kink modification and δ = 7.63 × 10⁻⁷ A without kink modification at V_GS = 1.00 V.

Gate Bias	kN (A/V2)	Vth (V)	λ	α (A)	β (V−2)	χ (V)
VGS = 0.25 V	9.50 × 10−5	−0.120	0.140	5.95 × 10−7	25.0	0.33
VGS = 0.50 V	8.73 × 10−5	−0.098	0.095	8.90 × 10−7	7.0	0.44
VGS = 0.75 V	7.78 × 10−5	−0.065	0.078	1.09 × 10−6	5.0	0.56
VGS = 1.00 V	7.07 × 10−5	−0.007	0.079	1.22 × 10−6	6.0	0.68

Table 3

Determined parameters of MOSFET L180 (length = 180 nm).

Gate Bias	kN (A/V2)	Vth (V)	λ	α (A)	β (V−2)	χ (V)
VGS = 0.80 V	0.228	0.556	0.170	7.78 × 10−4	46.0	0.22
VGS = 1.00 V	0.240	0.654	0.120	1.44 × 10−3	40.0	0.3
VGS = 1.20 V	0.234	0.759	0.090	1.95 × 10−3	35.0	0.38
VGS = 1.50 V	0.220	0.931	0.070	2.45 × 10−3	16.0	0.48
VGS = 1.80 V	0.197	1.101	0.062	2.51 × 10−3	13.0	0.6
VGS = 2.00 V	0.189	1.225	0.055	3.11 ×10−3	10.0	0.64
VGS = 2.20 V	0.177	1.345	0.056	3.01 × 10−3	9.0	0.7
VGS = 2.50 V	0.155	1.505	0.051	4.02 × 10−3	5.0	0.78

Table 4

Determined parameters of MOSFET L90 (length = 90 nm).

Gate Bias	kN (A/V2)	Vth (V)	λ	α (A)	β (V−2)	χ (V)
VGS = 0.80 V	5.000 × 10−4	0.3772	0.0280	2.40 × 10−6	16.0	0.40
VGS = 1.00 V	4.530 × 10−4	0.3980	0.0220	3.22 × 10−6	11.0	0.56
VGS = 1.20 V	3.950 × 10−4	0.3905	0.0184	3.90 × 10−6	11.0	0.74
VGS = 1.50 V	3.150 × 10−4	0.3215	0.0155	5.13 × 10−6	6.0	1.04
VGS = 1.80 V	2.400 × 10−4	0.1345	0.0140	6.53 × 10−6	4.0	1.40
VGS = 2.00 V	2.000 × 10−4	−0.0630	0.0145	8.76 × 10−6	1.4	1.60
VGS = 2.20 V	1.680 × 10−4	−0.1700	0.0270	1.20 × 10−5	1.4	1.78

Table 5

Determined parameters of FinFET at V_GS = 1.00 V without adjustment of kink effect.

Gate Bias	kN (A/V2)	Vth (V)	λ	χ (V)	δ (A)
W120L100	1.50 × 10−4	0.001	0.310	NA	4.36 × 10−7
W120L160	1.26 × 10−4	−0.1065	0.170	NA	9.58 × 10−7
W120L240	1.09 × 10−4	0.097	0.130	NA	3.88 × 10−7
W120L2000	7.07 × 10−5	−0.007	0.079	NA	7.63 × 10−7

References

1. Diab, A.; Torres Sevilla, G.-A.; Christoloveanu, S.; Hussain, M.-M. Room to high temperature measurements of flexible SOI FinFETs with sub-20-nm fins. IEEE Trans. Electron. Devices; 2014; 61, 3978. [DOI: https://dx.doi.org/10.1109/TED.2014.2360659]

2. Wang, F.; Xie, Y.; Bernstein, K.; Luo, Y. Dependability analysis of nano-scale FinFET circuits. Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI’06); Karlsruhe, Germany, 2–3 March 2006; 6-pp.

3. Huang, X.; Lee, W.-C.; Kuo, C.; Hisamoto, D.; Chang, L.; Kedzierski, J.; Anderson, E.; Takeuchi, H.; Choi, Y.-K.; Asano, K. et al. Sub-50 nm P-channel FinFET. IEEE Trans. Electron. Devices; 2001; 48, 880. [DOI: https://dx.doi.org/10.1109/16.918235]

4. Rudenko, T.; Kilchytska, V.; Arshad, M.K.M.; Raskin, J.-P.; Nazarov, A.; Flandre, D. On the MOSFET Threshold Voltage Extraction by Transconductance and Transconductance-to-Current Ratio Change Methods: Part II-Effect of Drain Voltage. IEEE Trans. Electron. Devices; 2011; 58, pp. 4180-4188. [DOI: https://dx.doi.org/10.1109/TED.2011.2168227]

5. Takahashi, T.; Beppu, N.; Chen, K.; Oda, S.; Uchida, K. Self-heating effects and analog performance optimization of Fin-type field-effect transistors. Jpn. J. Appl. Phys.; 2013; 52, 04CC03. [DOI: https://dx.doi.org/10.7567/JJAP.52.04CC03]

6. Saitoh, M.; Yasutake, N.; Nakabayashi, Y.; Uchida, K.; Numata, T. Understanding of strain effects on high-field carrier velocity in (100) and (110) CMOSFETs under quasi-ballistic transport. Proceedings of the 2009 IEEE International Electron Devices Meeting (IEDM), Baltimore, MD, USA; Baltimore, MD, USA, 7–9 December 2009; pp. 1-4.

7. Chen, C.W.; Wang, S.J.; Hsieh, W.C.; Chen, J.M.; Jong, T.; Lan, W.H.; Wang, M.C. Q-factor Performance of 28 nm-node High-k Gate Dielectric under DPN Treatment at Different Annealing Temperatures. Electronics; 2020; 9, 2086. [DOI: https://dx.doi.org/10.3390/electronics9122086]

8. Lu, P.; Yang, C.; Li, Y.; Li, B.; Han, Z. Three-Dimensional TID Hardening Design for 14 nm Node SOI FinFETs. Eng; 2021; 2, pp. 620-631. [DOI: https://dx.doi.org/10.3390/eng2040039]

9. Song, Y.S.; Tayal, S.; Rahi, S.B.; Kim, J.H.; Upadhyay, A.K.; Park, B.-G. Thermal-Aware IC Chip Design by Combining High Thermal Conductivity Materials and GAA MOSFET. Proceedings of the 2022 5th International Conference on Circuits, Systems and Simulation (ICCSS); Nanjing, China, 13–15 May 2022; pp. 135-140.

10. Crupi, G.; Schreurs, D.M.M.-P.; Caddemi, A.; Angelov, I.; Homayouni, M.; Raffo, A.; Vannini, G.; Parvais, B. Purely analytical extraction of an improved nonlinear FinFET model including non-quasi-static effects. Microelectron. Eng.; 2009; 86, pp. 2283-2289. [DOI: https://dx.doi.org/10.1016/j.mee.2009.04.006]

11. Li, Y.; Zhao, F.; Cheng, X.; Liu, H.; Zan, Y.; Li, J.; Zhang, Q.; Wu, Z.; Luo, J.; Wang, W. Four-Period Vertically Stacked SiGe/Si Channel FinFET Fabrication and Its Electrical Characteristics. Nanomaterials; 2021; 11, 1689. [DOI: https://dx.doi.org/10.3390/nano11071689] [PubMed: https://www.ncbi.nlm.nih.gov/pubmed/34203194]

12. Zhao, E.; Zhang, J.; Salman, A.; Subba, N.; Chan, J.; Marathe, A.; Beebe, S.; Taylor, K. Reliability challenges of high performance PD SOI CMOS with ultra-thin gate dielectrics. Solid State Electron.; 2004; 48, pp. 1703-1708. [DOI: https://dx.doi.org/10.1016/j.sse.2004.05.003]

13. Zhao, Z.Q.; Li, Y.; Zan, Y.; Li, Y.L.; Li, J.J.; Cheng, X.H.; Wang, G.L.; Liu, H.Y.; Wang, H.X.; Zhang, Q.Z. et al. Fabrication technique of the Si_0.5Ge_0.5 Fin for the high mobility channel FinFET device. Semicond. Sci. Technol.; 2020; 35, 045015. [DOI: https://dx.doi.org/10.1088/1361-6641/ab74f1]

14. Lee, J.; Park, T.; Ahn, H.; Kwak, J.; Moon, T.; Shin, C. Prediction Model for Random Variation in FinFET Induced by Line-Edge-Roughness (LER). Electronics; 2021; 10, 455. [DOI: https://dx.doi.org/10.3390/electronics10040455]

15. Van Zeghbroeck, B. Priciples of Semiconductor Devices, Chapter 7.6 Advanced MOSFET Issues. Available online: https://truenano.com/PSD20/chapter7/ch7_6.htm (accessed on 28 February 2002).

16. Yang, H.-C.; Chi, S.-C. Process Corresponding Implications Associated with a Conclusive Model-Fit Current-Voltage Characteristic Curves. Appl. Sci.; 2022; 12, 462. [DOI: https://dx.doi.org/10.3390/app12010462]

17. Yang, H.-C.; Chi, S.-C.; Liao, W.S. Comparison of Fitting Current–Voltage Characteristics Curves of FinFET Transistors with Various Fixed Parameter. Appl. Sci.; 2022; 12, 10519. [DOI: https://dx.doi.org/10.3390/app122010519]

18. Ryder, L.H. The sine-Gordon kink. Quantum Field Theory; Press Syndicate of the University of Cambridge: Cambridge, UK, 1985; 402.

19. Lacroix, D.; Traore, I.; Fumwron, S.; Jeandel, G. Phonon transport in silicon, influence of the dispersion properties choice on the description of the anharmonics resistive mechanisms. Eur. Phys. J. B; 2009; 67, pp. 15-25. [DOI: https://dx.doi.org/10.1140/epjb/e2008-00464-6]

20. Kang, S.-M.; Leblebici, Y. CMOS Digital Integrated Circuits: Analysis and Design, Chapter 4 Modeling of MOS Transistors Using SPICE; McGRAW-Hill: New York, NY, USA, 1996; 111. ISBN 0-07-114423-4

21. Yang, H.-C.; Chi, S.-C. Conclusive Model-Fit Current Voltage Characteristic Curves with Kink Effects. Appl. Sci.; 2023; 13, 12379. [DOI: https://dx.doi.org/10.3390/app132212379]

22. Yang, H.-C.; Tsai, J.-M.; Chang, T.-Y.; Liao, W.-S.; Chi, S.-C. The Effects of Thickness of Source/Drain Fin on P-Channel FinFET Devices and the Corresponding Quantum Effects. Nanosci. Nanotechnol. Lett.; 2014; 6, pp. 165-169. [DOI: https://dx.doi.org/10.1166/nnl.2014.1674]