1. Introduction
In recent years, the active-matrix organic light-emitting diode (AMOLED) has become an important device with various applications in devices, such as smartphones, smartwatches and TVs, due to its numerous advantages [1,2]. In an AMOLED display, while video signals are applied to each pixel in the form of voltage, the magnitude of light emitted by each pixel is determined by the driving current flowing through an OLED. The voltage-to-current conversion process is conducted by a thin-film transistor (TFT) in each pixel. This TFT is generally referred to as a driving TFT. Two major requirements for the driving TFT are high field effective mobility and robust stability. Various TFT technologies have been suggested for AMOLED displays [3,4]. In particular, in mobile applications, low-temperature polycrystalline silicon (LTPS) TFTs have mainly been used as a stable current driver. Although LTPS TFTs have relatively good stability compared to other TFTs, their non-uniformity in electrical characteristics has been a critical concern [5,6]. When the characteristics of LTPS TFTs are not sufficiently uniform, uneven brightness in display images can occur as a result of the voltage-to-current conversion process. Therefore, a specific pixel circuit should be designed to compensate for the LTPS TFTs’ non-uniformity [7,8,9].
The conventional compensation circuit of seven TFTs and one capacitor (7T1C) pixel circuit shown in Figure 1 was designed to compensate for threshold voltage (VT) variations in LTPS TFTs [10]. In the early stage of AMOLED development over the past 10 years, the maximum current level of OLED in a pixel was higher than a few micro amperes, and the operating regime of the driving TFT was the saturation regime. Therefore, the 7T1C pixel circuit was quite effective in compensating for the VT variation and relieving the uneven display image which originated from the non-uniform device characteristics.
Recently, the AMOLED resolution of smartphones has significantly increased, and the emission efficiency of OLEDs has also been improved [11,12]. As shown in Table 1, the maximum current level of a green pixel is as low as about 25 nA in a 600 ppi (pixel per inch) smartphone. The efficiency values of OLEDs in Table 1 were extracted from the actual test cells, and the maximum OLED current values were calculated based on those efficiency values to meet the typical brightness and white balance specifications of smartphones. The current level of 25 nA is obtained under the subthreshold regime of the driving TFT, and the magnitude of the current is exponentially proportional to the gate-to-source voltage (VGS) minus VT under that regime. This means that a very small error in the voltage applied to the driving TFT can elevate the current error rate (CER) considerably during the voltage-to-current conversion process. Therefore, it is necessary to investigate the performance of a 7T1C pixel circuit in view of the CER under the modern circuit driving conditions, that is, under conditions where the driving TFT operates under the subthreshold regime. The electrical characteristics of LTPS TFTs cannot be represented by only one parameter, VT. In addition to the variation in VT, variations in other important parameters such as sub-threshold swing (SS), carrier mobility (μ0) and the capacitive coupling effect should be investigated in view of their influence on the CER.
In this work, we analyzed the influence of various TFT parameters on the CER based on the 7T1C pixel circuit. This study was conducted using SPICE simulation results and the measured electrical characteristics of LTPS TFTs.
2. Operation of Compensation Circuit
The 7T1C pixel circuit can be classified as a diode-connection-type circuit and mainly compensates for the variation in VT in the driving TFT (T1) in Figure 1.
The operational process of the 7T1C pixel circuit consists of three steps. These three steps are distinguished by the state of three control signals: Scan[n-1], Scan[n] and En[n] (as shown in Figure 1b). During the first step, when only Scan[n-1] is low, the voltage of the storage capacitor (CST) is reset by the initial voltage. During the second step, when only Scan[n] is low, the VT extraction of T1 and data writing are simultaneously performed. During the third step, when only Em[n] is low, T1 generates the current, which flows through an OLED and is proportional to the amount of emitted light. This final step is the so-called emission period, which takes up nearly the whole frame period. The second step among the three steps should be intensively analyzed from the viewpoint of the difference in T1’s gate node voltage (VG) among pixels, which is directly related to the CER.
Figure 2 illustrates how the variation in VT can be eliminated during the second step in 7T1C pixel circuit operation. At this moment, T3 and T4 are turned on, so that T1 enters the diode-connection state, as shown in Figure 2. In the diode-connection state, T1’s VG rises until T1 is turned off, so VG approaches the level of VData plus T1’s VT, approximately. Strictly speaking, at the end of the second step, the state of T1 is not in the turn-off state but in the subthreshold regime. At this instant, the drain current becomes significantly low; however, this current value would not be the same among all pixels. This is one of the significant origins of the imperfection in the 7T1C pixel circuit in compensating for the variation in VT. At the end of the second step, another factor affects T1’s VG through the switch TFT, T4. At the end of the second step, T4’s gate node voltage suffers a considerable swing from the turn-on level to turn-off level. This abrupt change can induce the change in T4’s drain node voltage, which is also T1’s VG. One inducing mechanism is related to the charge injection, which originates from the elimination of T4’s channel charges. Another inducing mechanism is related to capacitive coupling via the parasitic capacitance between T4’s gate and T4’s drain.
Figure 3 shows the simulation result of the VG change along the elapsed time, which covers all three operational steps of the 7T1C pixel circuit. In this simulation, the duration of the second step, T1’s VT, and VData are set to be 5.2 μs, −1.3 V and 3.9 V, respectively. In Figure 3, T1’s gate node voltage is marked with two different notations, VG1 and VG2, in order to distinguish before and after the instance of T4’s state change from turn on to turn off. The simulation result shows that the 7T1C circuit extracts T1’s VT as about −1.8 V. This value is deduced from VG1 minus VData (=VGS of T1) at the end of the second step in 7T1C circuit operation. This moment corresponds to the time of 10.3 μs on the time axis of Figure 3. The extracted VT of T1 is somewhat different from its original value, which is assigned as the simulation input parameter, −1.3 V. This is because the duration of the second step is not long enough for T1’s VGS to approach the input value for VT. At around 10.3 μs, it can be also found that T1’s VG jumps from the VG1 level to the VG2 level. This is due to the abovementioned charge injection effect and capacitive coupling effect induced by T4’s state change from turn on to turn off. Finally, the current level to drive the OLED during the emission period is determined by the VGS of T1 or VG2 minus VDD during the emission period.
3. Considerations for CER Simulation
Even though the same VData is applied to all pixels and the duration of the second step is extended within the actual limit (<20 H, 1H = duration of scanning one horizontal line), the previously mentioned two events do not proceed exactly in the same way for every pixel. One of the two events is T1’s CST charging action during the second step and the other is T4’s charge injection and capacitive coupling at the end of the second step. The parameters which are capable of affecting T1’s VG in these two events are summarized in Table 2.
The first event is mainly affected by T1’s charging capability. As discussed, the main purpose of the 7T1C pixel circuit is VT compensation, so a 7T1C pixel circuit cannot compensate for the variations in μ0 and SS. It is noticed that the carrier mobility and the subthreshold swing are incorporated in Table 2. If the duration of the second step in 7T1C circuit operation is sufficiently long, T1’s VG level of each pixel can be saturated to a proper VT variation-compensated value. However, in commercial applications and especially in the case of high-resolution displays, the duration time (<20 H) of the second step is insufficient to eliminate the variation in VT among all pixels. Therefore, we should investigate the effects of the variation in μ0, SS and parasitic capacitance on the performance of the 7T1C pixel circuit and should compare them with the effect of VT variation. The process parameters related to physical dimensions such as film thickness and pattern size rarely change among neighboring pixels in the range of a few millimeters. In industrial fabrication lines, these physical dimensions would vary very gradually, at most 5% of the variation rate over the whole substrate [13,14]. However, the TFT characteristics can abruptly change due to the grain structure of LTPS, as shown in Figure 4. The grain size of LTPS is about 0.4 μm on average. Therefore, the number of grains contained in the channel area of a TFT may vary for each pixel, considering that the channel area is in the micrometer order. It means that the characteristics of LTPS TFT such as VT, SS and μ0 can be significantly different among adjacent pixels, even in a short range.
In addition, we should consider another parameter related to TFT stability. Figure 5 shows the measured capacitance–voltage (C-V) curve of p-channel LTPS TFT after various accumulative time elapses of drain-bias stress. The minimum value of the capacitance between the gate and drain (i.e., CGDO) increases as the accumulative bias stress time increases, while the minimum value of the capacitance between the gate and source (i.e., CGSO) hardly changes. Even for the adjacent pixels, the CGDO value can vary due to different accumulative bias stress time.
Therefore, at the end of the second step in 7T1C circuit operation, when T4’s state changes from turn on to turn off, T4’s parasitic capacitance such as CGDO would be an important factor that could influence T1’s ΔVG (as shown in Figure 3). If CST is large enough, the coupling effect can be negligible. However, the influence of the coupling effect cannot be ignored due to the limited CST area in the case of a high-resolution display. For the circuit simulation, the pixel circuit including the variation in CGDO, as illustrated in Figure 6, is employed, and the variation in CGDO is treated as the factor that might affect the CER.
The simulation parameters are listed in Table 3 based on the considerations discussed above. The parameters related to physical dimensions in Table 3a are treated as constant values, and the six parameters in Table 3b are the variables. The SPICE model of TFT is the Rensselaer Polytechnic Institute (RPI) poly-Si TFT model. The simulation was conducted with Silvaco’s SmartSpice tool.
4. Simulation Results and Discussion
In order to investigate the influence of each parameter, SPICE simulations were carried out by varying only one parameter according to the deviation condition listed in Table 3. The other parameters were set as the median value. The CER was evaluated for five different gray levels. The lowest one was the 15th gray level. The 31st, 63rd, 127th and 255th gray levels were also included. The CER value was defined as the percentage of the current deviation from the target current, for each gray level.
Figure 7 shows the CER values obtained by the circuit simulations under various input parameter sets. In Figure 7, it can be found that the CER tends to increase as the gray level becomes lower, and the most significant factor that increases the CER is SS. The gray-level dependency of CER can be attributed to the fact that the incremental step of OLED currents between the adjacent gray levels becomes smaller as the gray level becomes lower. In other words, the very small error in voltage applied to the driving TFT results in higher CER in the low gray level than in the middle or the high gray level. The SS dependency of CER can be explained as follows. As mentioned previously, because the duration of the second step in 7T1C circuit operation is insufficient in general, VG cannot be fully saturated to an ideal value, which eliminates the variation in VT of the driving TFT among pixels. Especially in the later part of the second step, the diode-connected driving TFT generates current for charging CST in the subthreshold regime, so different SS values determine the amount of the deviation from T1’s ideal VG value, which can eliminate the VT variation perfectly. Consequently, the most significant factor to increase the CER is SS.
The second significant factor is the CGDO of T4. Figure 7 shows that the CGDO of T4 mainly affects the CER. It should be noted that the variation in CGDO can occur via drain bias stress, as shown in Figure 5, so device stability should also be guaranteed. The third significant factor is T1’s VT. This is related to the imperfection of 7T1C circuit operation in compensating for the variation in T1’s VT due to the limited duration of the second step. The fourth significant factor is T4’s VT. T4’s VT is also related to the amount of capacitive coupling at the end of the second step. The amount of capacitive coupling is proportional to the amount of T4’s VG change as well as CGDO size. To be exact, the amount of T4’s VG change related to the capacitive coupling is the VG change from the VT level to the turn-off level. Therefore, the variation in T4’s VT indirectly affects the CER via capacitive coupling.
In order to investigate the effect of T1’s SS in detail, we compared the CER for two extreme cases, high SS of 0.55 V/dec and low SS of 0.25 V/dec, respectively. For each case, other parameters were varied in the same manner as listed in Table 3b, except the SS variation. Table 4 shows the comparison results of the low SS case and the high SS case for T1. Table 4 clearly shows that the CER caused by other parameter variations can be dramatically reduced if the SS is increased.
In order to explain the above results, we checked how much data voltage is required for each gray level in the case of low SS and high SS. As shown in Figure 8, the range of required data voltages in the high SS case is wider than that in the low SS case, which means that the data voltage difference between two adjacent gray levels increases and that the sensitivity of CER caused by the variation in other device parameters can be reduced.
The effect of SS variation itself in the high SS case was also investigated and compared with that of the low SS case. Two sets of simulation conditions were designed for the comparison. The first input parameter set was designed to compare the effect of the same variation rate between the high SS of 0.55 V/dec and low SS of 0.25 V/dec. The variation rate was selected as ±10%. Table 5a shows the simulation results. In Table 5a, the CER represents the average value of the CERs calculated at +10% variation and at —10% variation. Although the absolute variation value in the high SS case is about two-times larger than that in the low SS case, the CER in the high SS case is not so high, as compared with that in the low SS case.
The other input parameter set was designed to compare the effect of the same variation value between the high SS of 0.55 V/dec and low SS of 0.25 V/dec. The variation value was selected as ±0.025 V/dec, which is ±10% variation of the low SS value. In Table 5b, the CER represents the average value of the CERs calculated at + 0.025 V/dec variation and at—0.025 V/dec variation. In Table 5b, it can be seen that the CER in the high SS case is considerably lower than that in the low SS case, especially in the middle and high gray levels. These results can be explained by the abovementioned difference in the required data voltage range for the gray expression between the high SS case and the low SS case. The above simulation results indicate that the SS value should be high, and its variation should be low in order to reduce the CER. However, it should be checked whether the variation in SS can be suppressed as its value becomes higher. Figure 9 shows fourteen TFT characteristics for the low SS case (Figure 9a) and high SS case (Figure 9b). The characteristics with the low SS were obtained by applying hydrogen plasma treatment. After hydrogen plasma treatment, the variation in SS also decreases while the SS becomes low. The subthreshold slope of a TFT is closely related to two main properties: the capacitance of the gate insulator and the density of interface states [15]. The above hydrogen plasma treatment experiments indicate that the SS value and its variation reduce at the same time as the density of the gate insulator interface states gets lower. Therefore, in order to obtain both goals, the high SS and its small variation, the interface states of the gate insulator should be lowered through an optimized surface treatment such as hydrogen plasma treatment in order to reduce the variation in SS. In addition, the reduced SS value due to the surface treatment should be compensated for through elaborate control of the gate insulator thickness. Therefore, the gate insulator thickness should be high enough to obtain the required high SS value, which guarantees the low CER.
5. Conclusions
In this research, we found that the CER significantly rises in the conventional 7T1C AMOLED pixel circuit when dealing with low gray levels. The origin for the high CER can be categorized in two key factors. One is the charging capability of the driving TFT under the subthreshold regime and the other is the capacitive coupling of the switching TFT. Our SPICE simulation results show that the SS of the driving TFT is one major factor affecting the CER, and the second major factor is the variation in the parasitic capacitance of the switching TFT.
The SS of the driving TFT is the most effective parameter to control the CER. In addition, the high SS value makes the sensitivity of CER on the variation of other device parameters lower. In conclusion, in order to minimize the CER caused by the deviation of TFT characteristics, it is most important that TFTs should be fabricated to exhibit a high SS value and small SS variation.
Conceptualization, K.C.M. and K.P.; software, K.C.M.; validation, J.-H.J.; investigation, K.P.; writing—original draft, K.C.M.; writing—review and editing, J.-H.J. and K.P. All authors have read and agreed to the published version of the manuscript.
The original contributions presented in this study are included in the article. Further inquiries can be directed to the corresponding authors.
The authors declare no conflicts of interest.
Footnotes
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Enlarge this image.Figure 1. Conventional 7T1C AMOLED pixel circuit: (a) circuit diagram; (b) timing diagram.
Enlarge this image.Figure 3. Simulation result of T1’s VG change during 7T1C pixel circuit operation.
Enlarge this image.Figure 5. C-V characteristics of p-channel TFT after drain-bias stress: (a) gate–source capacitance (CGS); (b) gate–drain capacitance (CGD).
Enlarge this image.Figure 7. Simulation results of the CER for various gray levels under the conditions in Table 3.
Enlarge this image.Figure 8. Required data voltages for various gray levels in the low SS case and the high SS case.
Enlarge this image.Figure 9. Measured LTPS TFT characteristics showing different gate insulator interface properties (W/L = 10.5/3.5 μm, VDS = 10 V, Tox = 150 nm): (a) showing low SS; (b) showing high SS.
Efficiency and maximum current of OLED in a pixel.
| Green | Red | Blue | ||
|---|---|---|---|---|
| Efficiency (cd/A) | 150 | 45 | 5 | |
| Maximum OLED current (nA) | 400 ppi | 41 | 50 | 128 |
| 600 ppi | 25 | 30 | 80 | |
Parameters related to T1’s VG variation among pixels.
| Factor | Element | Parameter |
|---|---|---|
| T1’s CST charging action | CST | Dimension, Thickness of insulator |
| T1 | Dimension, Thickness of insulator, Threshold voltage, Carrier mobility, Subthreshold swing, Parasitic capacitance | |
| T4’s charge injection and capacitive coupling | CST | Dimension, Thickness of insulator |
| T4 | Dimension, Thickness of insulator, Threshold voltage, Parasitic capacitance |
Simulation parameters: (a) references; (b) parameter variation rules.
| (a) | ||
| Element | Dimension (W/L) | Parameters |
| T1 | 3.5/18.5 μm | VT = −1.3 V |
| T2 | 2.5/3.5 μm | |
| T3 | 2.5/3.5 μm | |
| T4 | 2.5/(3.5 + 3.5) μm | |
| T5 | 2.5/(3.5 + 3.5) μm | |
| T6 | 2.5/3.5 μm | |
| T7 | 2.5/3.5 μm | |
| CST | 40 fF | |
| (b) | ||
| Element | Parameter Variation | |
| T1 | VT = −1.3 ± 0.3 V | |
| μ0 = 90 ± 5 cm2/Vsec | ||
| CGDO = 450 ± 50 pF/m | ||
| T2 | VT = −1.3 ± 0.3 V | |
| CGDO = 450 ± 50 pF/m | ||
W (L): Channel width (length), Tox: Thickness of gate oxide.
Simulation results of the CER under the low and high SS cases (without SS variation).
| Gray Level | CER (%) by | CER (%) by | CER (%) by | |||
|---|---|---|---|---|---|---|
| @ SS = 0.25 (V/dec) | @ SS = 0.55 (V/dec) | @ SS = 0.25 (V/dec) | @ SS = 0.55 (V/dec) | @ SS = 0.25 (V/dec) | @ SS = 0.55 (V/dec) | |
| 255 | 6.6 | 4.9 | 0.9 | 0.8 | 3.2 | 2.9 |
| 127 | 8.3 | 11.7 | 4.7 | 9.9 | 6.9 | 3.5 |
| 63 | 11.4 | 14.5 | 5.2 | 11.3 | 10.9 | 5.3 |
| 31 | 34.8 | 17.6 | 32.0 | 11.7 | 17.2 | 7.3 |
| 15 | 48.7 | 30.8 | 36.8 | 17.7 | 26.3 | 8.5 |
Comparison of the CERs between the high SS case and the low SS case: (a) caused by the same variation rate of ±10%; (b) caused by the same variation value of ±0.025 V/dec.
| (a) | |||||
| Gray Level | OLED Current (A) | CER (%) by SS Variation | |||
| @ SS = 0.495 (V/dec) | @ SS = 0.55 (V/dec) | @ SS = 0.605 (V/dec) | @ SS = 0.55 ± 0.55 × 10% (V/dec) | @ SS = 0.25 ± 0.25 × 10% (V/dec) | |
| 255 | 2.6 × 10−8 | 2.5 × 10−8 | 2.37 × 10−8 | 9.0 | 7.1 |
| 127 | 4.65 × 10−9 | 5.43 × 10−9 | 5.59 × 10−9 | 17.3 | 16.8 |
| 63 | 8.8 × 10−10 | 1.18 × 10−9 | 1.38 × 10−9 | 42.0 | 32.1 |
| 31 | 1.85 × 10−10 | 2.56 × 10−10 | 3.07 × 10−10 | 47.7 | 38.9 |
| 15 | 3.26 × 10−11 | 5.65 × 10−11 | 8.87 × 10−11 | 99.2 | 52.4 |
| (b) | |||||
| Gray Level | OLED Current (A) | CER (%) by SS Variation | |||
| @ SS = 0.525 (V/dec) | @ SS = 0.55 (V/dec) | @ SS = 0.575 (V/dec) | @ SS = 0. 55 ± 0. 025 (V/dec) | @ SS = 0.25 ± 0. 025 (V/dec) | |
| 255 | 2.55 × 10−8 | 2.5 × 10−8 | 2.42 × 10−8 | 5.4 | 7.1 |
| 127 | 4.78 × 10−9 | 5.43 × 10−9 | 5.43 × 10−9 | 11.9 | 16.8 |
| 63 | 1.07 × 10−9 | 1.18 × 10−9 | 1.29 × 10−9 | 19.1 | 32.1 |
| 31 | 2.15 × 10−10 | 2.56 × 10−10 | 3.03 × 10−10 | 34.4 | 38.9 |
| 15 | 4.17 × 10−11 | 5.65 × 10−11 | 7.83 × 10−11 | 56.8 | 52.4 |
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Details
; Jae-Hong, Jeon 2
; Park, KeeChan 3
1 College of Information and Communication Engineering, Sungkyunkwan University, Suwon 16419, Republic of Korea;
2 School of Electronics and Information Engineering, Korea Aerospace University, Goyang 10540, Republic of Korea
3 School of Electrical and Electronics Engineering, Konkuk University, Seoul 05029, Republic of Korea