A Novel Architecture for Addressing the Throughput Bottleneck in Spaceborne Solid-State Recorder for Electromagnetic Spectrum Sensors

Abstract

The data acquisition rate of electromagnetic spectrum sensors is exceedingly high. However, the throughput of current high-speed spaceborne solid-state recorders (S-SSR) remains relatively low, making it difficult for the data to be fully stored. To address this issue, a novel architecture for a high-speed S-SSR is introduced in this study. The throughput of the S-SSR is primarily limited by three factors: the performance of the error-checking algorithm, the inability of a single FPGA to support the parallel expansion of too many Flash chips due to its limited effective I/O pins, and the efficiency of FLASH control. In the proposed architecture, a 10-stage pipelined RS(252,256) code is implemented. Data are distributed and stored in different memory regions controlled by separate FPGAs. Interleaved storage, multi-plane, and cache operation FLASH control module are also employed to resolve these bottlenecks. To further increase the throughput of the S-SSR, the system clock distribution has been optimized. In addition, interleaved encoding technology has been applied to improve radiation resistance and ensure data integrity. The performance of the system was evaluated on the Xilinx XC7K325T platform. The results confirm that the architecture is capable of handling high data rates and effectively correcting errors. The system can achieve a throughput of 46.8948 Gbps, making it suitable for future deployment in space exploration missions.

1. Introduction

Electromagnetic spectrum sensing is a crucial task in space scientific and technological domains, encompassing a broad range of frequencies from radio waves to gamma rays. The primary objective of electromagnetic spectrum sensing is to detect, identify, and analyze electromagnetic signals present in the environment. This capability is pivotal in applications such as space-based radar systems [1,2], astronomy [3], and space spectrum management [4,5,6]. Complete satellite spectrum monitoring data are crucial for designing and evaluating effective sensing algorithms. Despite advancements in spectrum sensing technologies, the current state-of-the-art in satellite-based spectrum sensing faces challenges due to incomplete monitoring data [7]. This problem primarily arises from inadequate storage capacities of Spaceborne Solid-State Recorders (S-SSRs). When storage rates are insufficient, the trade-off of discarding some data to reduce the required storage bandwidth results in the inability to obtain complete datasets. Additionally, Single-Event Upsets (SEU) and Multiple-Event Upsets (MEU) [8] can introduce errors in the data, further contributing to its incompleteness.

S-SSRs [9,10,11,12,13] typically consist of a data multiplexing unit, Error Correction Code (ECC) encoder, DDR high-speed cache, and FLASH control unit. The data multiplexing unit effectively processes multiple inputs from various IC, organizing them into standardized data packets for error checking and subsequent storage. The ECC encoder transforms the original data into a coded format that includes additional redundancy, enabling the detection and correction of errors that may occur during data transmission or storage. The FLASH control unit is employed for operating FLASH memory, including read, program, and erase functions. The demand for high-speed data storage driven by wideband transceiver IC is increasing significantly. However, the storage rate of S-SSR systems is constrained by three critical factors: the performance of the error-checking algorithm, the inability of a single FPGA to support the parallel expansion of too many Flash chips due to its limited effective I/O pins, and the efficiency of FLASH control. Compared to the speed of the DDR high-speed cache, the current maximum speeds of ECC encoding and FLASH writing are considerably lower.

In response to these bottlenecks, current research has made progress in addressing the following issues:

• Reed–Solomon (RS) codes [14] are commonly employed in ECC. The mainstream approach to implementing RS encoders involves optimizing operations over finite fields, simplifying complex multiplications and additions into shift and XOR operations [15]. When implemented in hardware, several to a dozen XOR operations are typically present in the critical path. This approach ensures that the critical path remains short, enabling high operating frequencies [16]. However, a single redundant error correction technique can effectively counter SBU but struggles to effectively mitigate MBU.

• In the field of data error correction, techniques such as RS codes and Hamming codes [17] are commonly employed. However, interleaving technology [18] can also be utilized to enhance error correction capabilities. By rearranging the data sequence prior to storage, the issue of ECC failure due to MBU can be effectively mitigated. Data from different ECC sequences are interleaved and stored in adjacent cells, so when consecutive bit flips occur due to radiation, the errors will be dispersed across multiple ECC sequences rather than confined to a single sequence. This distribution of errors reduces the burden on any single ECC sequence, thereby improving the overall effectiveness of error correction.

• Parallel expansion technology [19] is used to extend data bus bandwidth, enabling large-scale parallel data operations. This enhances overall system efficiency. In this approach, the data pins of multiple FLASH chips are connected in parallel and control signals are shared across these chips. As a result, a wider data bus is created. This allows multiple bits of data to be read from or written to the memory at the same time. The bandwidth available for data transmission is significantly increased, enabling faster data handling in high-performance applications. This method is regarded as cost-effective. Throughput can be increased by simply adding more FLASH chips and using additional FPGA pins. However, the method becomes ineffective once the required number of pins for the FLASH chips exceeds the available FPGA pins.

• In Multi-Level Cell (MLC) FLASH [20], multi-plane commands [21] and cache commands [22] are employed to enhance performance and efficiency. Multi-plane commands are designed to execute identical operations across multiple planes simultaneously. A plane in NAND flash memory is a subdivision of a die, and each die can contain multiple planes. The primary operations performed by multi-plane commands include program, read, and erase functions. By allowing these operations to occur concurrently across different planes, the overall performance of FLASH is substantially enhanced. Cache commands are employed to optimize data transfer between the host and the FLASH memory. By using a cache register, data can be temporarily stored, enabling subsequent commands to be executed without waiting for the previous ones to complete. At the system level, multi-chip configurations [23] have become mainstream because they allow for interleaved operations [24] across multiple sets of chips, significantly increasing the read and write throughput of multi-chip storage systems.

Based on current technological trends, a novel S-SSR architecture for storing electromagnetic spectrum data is proposed. This architecture optimizes both the ECC encoder and the FLASH control unit to increase the throughput of the ECC encoder and the data program speed of the FLASH control unit, addressing the demands of high-speed storage. Furthermore, a combination of ECC technology and data interleaving is employed in this architecture to ensure reliable operation in the presence of MBU encountered in space environments.

To optimize the ECC encoder, the architecture employs an ECC array composed of sixteen 8-bit wide RS(256,252) [25] encoders. The advantage of using a lower bit width lies in the fact that the critical path of RS(256,252) is determined by the bit width. The smaller the bit width, the shorter the critical path. With an 8-bit width, the critical path consists of three XOR operations, allowing RS(256,252) to operate at a higher frequency. To further enhance the operating frequency, a ten-stage pipeline implementation of the RS(256,252) algorithm is employed. This pipelining technique [26] divides the encoding process into smaller stages, enabling multiple operations to be processed concurrently.

Parallel expansion technology is an effective means of increasing FLASH throughput. However, due to the limited number of I/O pins on the FPGA, excessive parallel expansion of FLASH chips cannot be supported. To address this issue, the architecture employs a distributed storage approach. Multiple FPGAs independently control several storage areas, and these FPGAs along with their controlled storage areas are referred to as independent storage units. After data have been appropriately processed, they are transmitted to the storage units for storage via GTX transceivers [27]. By expanding the number of FPGAs, the available I/O pins are effectively increased, thereby further supporting the parallel expansion of additional FLASH chips.

In optimizing the FLASH control unit, the challenge lies in enhancing the program efficiency of the FLASH control unit, which involves achieving higher FLASH program speeds with fewer I/O pins. Combining chip-level cache and multi-plane technology can increase the read and program speeds of FLASH without increasing the number of I/O pins used. Integrated multi-chip technology takes this a step further by reusing address, data, and control lines across multiple chips, introducing additional chip select signals for interleaved operations. Combining cache, multi-plane, and multi-chip technologies, a four-stage pipeline method for FLASH program operations is proposed. This integrated approach ensures that the FLASH control unit can achieve higher program speeds while utilizing fewer I/O pins.

In summary, the major contributions of this research are as follows:

• To increase the operating frequency of the ECC encoder, multiple small-width RS(256,252) encoders are employed in parallel to form an ECC array that processes wide-width data. Additionally, a ten-stage pipeline architecture is implemented for the RS(256,252) algorithm, further enhancing the frequency.

• To overcome the limited number of I/O pins, a distributed storage approach is implemented. In this architecture, multiple FPGAs independently control various storage areas, collectively referred to as independent storage units. Processed data are transmitted to these storage units via GTX transceivers.

• To improve the program efficiency of the FLASH control unit, a four-stage pipeline method for FLASH program operations is proposed by integrating multi-plane, cache command, and multi-chip technologies.

• To further enhance the MBU resistance of the S-SSR architecture, an interleave unit is added between the ECC array and the DDR high-speed cache. This unit is responsible for interleaving ECC sequences, thereby more effectively dispersing potential errors and improving the overall reliability of the system.

The remainder of this paper is organized as follows. In Section 1, the proposed S-SSR architecture is described in detail. This section sequentially explains the optimization strategies for the ECC encoder and the FLASH control unit, providing a specific implementation of the interleaving unit. Experimental results and conclusions are presented in Section 2 and Section 3, respectively.

2. System Architecture

The core components of the system are composed of a data multiplexing unit, an ECC array, an interleaving unit, a DDR3 high-speed cache, a data distribution unit, GTX transceivers, and four storage units, as illustrated in Figure 1. The data multiplexing unit is responsible for converting data from its original format to a standardized 128-bit format. The data multiplexing unit is required to be designed in a tailored manner to meet specific task requirements. Common hardware interfaces and transceivers for the collection of electromagnetic spectrum data include LVDS, Serdes, TLK2711, and GT-class. Based on these interfaces and transceivers, upper-layer protocols such as 8b10b, 64b66b, Aurora, and JESD204 can be implemented. The relevant interfaces must be supported by the hardware devices, and the corresponding protocols must be supported by the data multiplexing unit to ensure compliance with task-specific demands. As long as the data rate is maintained below the rated storage capacity of the S-SSR system and sufficient storage space is provided, data loss will not occur. The ECC array comprises 16 parallel error control modules. These modules operate under the RS(256,252) algorithm to enhance data reliability. Each module processes 252 characters of 8-bit width. Additionally, four fault-tolerant control characters are added, resulting in an expansion of the data to 256 characters. This error-checking mechanism is capable of correcting or identifying errors in up to four characters. The interleaving unit interleaves the 16 8-bit error control sequences from the ECC array. This process significantly enhances data transmission security. The DDR3 cache operates at an 800 MHz I/O clock frequency and a 32-bit I/O width. It provides a maximum data transfer rate of 51.2 Gbps. The data distribution unit is utilized to distribute data read from the DDR3 SDRAM to multiple storage units via GTX transceivers. Each storage unit is composed of an FPGA and its controlled storage area. The Flash control unit is designated as the primary functional unit on this FPGA. It manages the transfer of data from the GTX transceiver to the Flash storage area.

The operational frequencies of various components are critically influential to the overall performance of the onboard storage system. The data multiplexing unit, ECC array, and interleaving unit are configured to operate at a frequency of 400 MHz. The DDR3 cache and data distribution unit are set to operate at 200 MHz. The GTX transceiver is operated at a clock frequency of 120 MHz, which provides a transmission bandwidth of 12 Gbps. This configuration is intended to reduce the number of modules in the ECC array and the scale of the interleaving unit. Higher frequency operations are utilized to optimize timing and power consumption. At the lower frequency of 200 MHz, the ECC array requires 32 parallel error control modules to meet the high-speed storage demands of the DDR3 cache while ensuring effective error checking. When the operational frequency of the ECC array is increased to 400 MHz, the processing capability of each module is doubled. Consequently, only 16 modules are required to maintain the same error control capability.

2.1. ECC Array

The ECC array within the system is composed of 16 error control modules that operate in parallel. Each module implements the RS(256,252) algorithm. This algorithm is recognized as an effective error control mechanism designed for code blocks with a length of 256 symbols. In each block, the first 252 symbols are designated as information bits. Each information bit consists of 8 bits, while the last four symbols are designated as check symbols.

The process of encoding input data using the RS(256,252) algorithm is initiated by shifting the input data, denoted as $m\left(x\right)$, left by four bits. The four least significant bits are padded with zeros. As a result, the original polynomial is transformed into $ml\left(x\right)$.

(1)$m\left(x\right)=(m_{251}{x}^{251}+\cdots +m_{1}x+m_0)$

(2) $ml\left(x\right)=m\left(x\right)\times x^4=m_{251}{x}^{255}+\cdots +m_1{x}^{2\prime +1}+m_0{x}^4+0x^3+\cdots +0x+0$

The next step involves computing the remainder of $ml\left(x\right)$ when divided by the generator polynomial $g\left(x\right)$. The resultant remainder $r\left(x\right)$ identifies the check bits required for error correction.

(3)$g\left(x\right)=x^8+x^4+x^3+x^2+1$

(4) $r\left(x\right)=ml\left(x\right)\%g\left(x\right)$

The encoded result $t\left(x\right)$ is obtained by adding $ml\left(x\right)$ to the remainder $r\left(x\right)$.

(5)$t\left(x\right)=ml\left(x\right)+r\left(x\right)$

The RS(256,252) algorithm is particularly noteworthy for its error correction capabilities. It is capable of correcting up to two erroneous symbols, provided that the condition $2E+S<=4$ is satisfied. In this equation, S represents the number of known error locations and E denotes the number of unknown error locations. This algorithm enhances the reliability of data transmission by ensuring data integrity. High levels of data accuracy and security are also supported by this algorithm. These factors are crucial for operations in challenging environments, such as space.

In the implementation of the RS(256,252) algorithm, the cyclic XOR method is employed to minimize path delay, as illustrated in Figure 2. The operational frequency of the error control module is set at 400 MHz. This process is organized into 10 pipeline stages, as shown in Figure 3. For output symbol counts less than 252, the pipeline is fixed at 5 stages. However, when an output symbol count of 252 is reached, an additional 5 stages are activated to compute and output the parity symbol. The pipeline is partitioned into distinct stages. This partitioning effectively reduces the complexity of combinational logic between adjacent registers. It also decreases path delays during layout. This structured approach enables precise timing to be maintained at the 400 MHz clock frequency. Additionally, a timing margin of 20% is allowed to accommodate variations in external circuit conditions.

Each error control module processes an 8-bit symbol per clock cycle and accumulates 252 symbols before sequentially outputting 4 parity symbols, as illustrated in the timing diagram in Figure 4. Within every 260 clock cycles, the module handles 252 data points of 8-bit symbols. With a clock cycle duration of 2.5 ns, the module operates at a rate of 3.101 Gbps, contributing to a total throughput of 49.624 Gbps for the ECC array.

2.2. Interleave Unit

Assuming that the output of the ECC array is represented by $t\left(x\right)$, which includes symbols from 16 ECC check sequences, as shown in Equation (6). The purpose of the interleave unit is to sufficiently interleave the output of the ECC array. This interleaving is performed to increase the distance between symbols within the same ECC sequence. When an MBU event occurs and insufficient spacing exists between symbols within the same ECC sequence, errors may be introduced in 2 to 3 consecutive symbols. This situation exceeds the maximum error correction capability of the ECC. As a result, ECC failure may occur. By increasing the spacing between symbols through interleaving, errors from an MBU event can be distributed across multiple ECC sequences. Consequently, each ECC sequence will encounter at most one symbol error. This distribution keeps the errors within the correction capability of the ECC.

(6)$t\left(x\right)=m_{15}{x}^{15}+m_{14}{x}^{14}+m_{13}{x}^{13}+m_{12}{x}^{12}\cdots +m_{1}x+m_0$

Four transformation methods—$t_1\left(x\right)$, $t_2\left(x\right)$, $t_3\left(x\right)$, and $t_4\left(x\right)$—are proposed for interleaving the ECC sequences, as shown in Equation (7). Sequentially transforming the symbol positions within $t\left(x\right)$ using $t_1\left(x\right)$, $t_2\left(x\right)$, $t_3\left(x\right)$, and $t_4\left(x\right)$ enables a spacing of 4 symbols. Specifically, upon obtaining the first $t\left(x\right)$ output from the ECC array, it is transformed into $t_1\left(x\right)$ and then outputted. Subsequently, after obtaining the second, third, and fourth outputs from the ECC array, each is transformed into $t_2\left(x\right)$, $t_3\left(x\right)$, and $t_4\left(x\right)$, respectively, and outputted sequentially. Thereafter, this process repeats with every four outputs forming a group, cyclically using the transformations $t_1\left(x\right)$, $t_2\left(x\right)$, $t_3\left(x\right)$, and $t_4\left(x\right)$.

(7)$\begin{array}{cc}\hfill t_1\left(x\right)& =m_{15}{x}^{15}+m_{14}{x}^{14}+m_{13}{x}^{13}+m_{12}{x}^{12}+\cdots +m_{1}x+m_0\hfill \\ \hfill t_2\left(x\right)& =m_{11}{x}^{11}+m_{10}{x}^{10}+\cdots +m_{1}x+m_0+m_{15}{x}^{15}+m_{14}{x}^{14}+m_{13}{x}^{13}+m_{12}{x}^{12}\hfill \\ \hfill t_3\left(x\right)& =m_7{x}^7+m_6{x}^6+\cdots +m_{1}x+m_0+m_{15}{x}^{15}+m_{14}{x}^{14}+\cdots +m_9{x}^9+m_8{x}^8\hfill \\ \hfill t_4\left(x\right)& =m_3{x}^3+m_2{x}^2+m_{1}x+m_0+m_{15}{x}^{15}+m_{14}{x}^{14}+\cdots +m_5{x}^5+m_4{x}^4\hfill \end{array}$

To ensure the data interleaving unit operates at a clock frequency of 400 MHz, a three-stage pipelined structure, depicted in Figure 5, is employed. Due to the 128-bit width of $t\left(x\right)$, selecting and outputting one transformation from four options within a single clock cycle would incur unacceptable logical delays. Hence, this selection process is divided into three clock cycles, forming a three-stage pipeline. The mux in the diagram serves as a selection unit, choosing between two inputs. Through the operation of the two-stage mux, $t_1\left(x\right)$, $t_2\left(x\right)$, $t_3\left(x\right)$, and $t_4\left(x\right)$ are sequentially selected and outputted.

A block of data, enhanced with parity symbols and interleaved according to the aforementioned method, consists of 252 data symbols and 4 parity symbols, derived from 16 parity control modules, as illustrated in Figure 6. In Figure 6, the notation $Y_{a,b}$ indicates that a represents the a-th parity control module, while b denotes the b-th symbol in the parity sequence. In the figure, the orange-highlighted positions indicate the occurrence of a single-bit upset event. This event occurs in the 11th parity sequence, where only one error is present, making it correctable. The purple-highlighted positions represent the occurrence of a double-bit upset event. This event affects the 1st and 2nd parity sequences, each containing a single error, both of which are correctable. The yellow-highlighted positions denote the occurrence of a triple-bit upset event. This event impacts the 4th, 5th, and 6th parity sequences, with each sequence containing only one error, all of which are correctable. The green-highlighted positions indicate a quadruple-bit upset event. This event affects the 7th, 8th, 9th, and 12th parity sequences, with each sequence having one error, all of which are correctable. Finally, the blue-highlighted positions signify a quintuple-bit upset event. This event occurs in the 3rd, 10th, 13th, 14th, and 15th parity sequences, with each sequence containing one error, all of which are correctable. If all of these error events occur simultaneously, the errors will be distributed across the 1st through the 15th parity sequences, with each sequence containing exactly one error. In such a scenario, the errors can still be fully corrected.

2.3. FLASH Control Unit

Interleaving, caching, and multi-plane operation are applied by the FLASH control unit to improve the performance and efficiency of the storage system. Interleaving increases access speed by enabling multiple memory chips to operate in a pipelined manner. During the programming process, data are first written into the cache area of the FLASH memory chip. Once the cache is full, the programming operation is initiated. At this point, data are transferred from the cache to the storage cells. By using interleaving, data can be written into the cache of another chip as soon as the first chip cache is filled. This does not require waiting for the first chip programming operation to complete. As a result, multiple chips are programmed simultaneously, enhancing overall system performance and efficiency. Multi-plane operation allows simultaneous programming across multiple planes within the same chip. Each plane has its own cache, enabling independent operations to take place at the same time. With multi-plane operation, one page of data is written into the cache of one plane while another page is written into the cache of a different plane. These pages are then programmed into the storage cells concurrently. This method doubles the data throughput of the chip without increasing the number of chips.

The FLASH storage area consists of 32 NAND FLASH chips. These chips provide a total effective storage capacity of 4 Tbit. Each chip is divided into four planes, and each plane can store 16 Gbit of data. The page size is 8 KB. The FLASH chips are divided into two groups that share a 128-bit wide data bus. Each group is activated by chip select signals, as shown in Figure 7. Specifically, when data equivalent to 64 pages are accumulated by the FLASH control unit, they are written into the cache registers of all planes in one group of FLASH chips. Each group consists of 16 FLASH chips, with each chip divided into 4 planes. Consequently, a total of $16*4=64$ pages is required to fill the cache registers of one group. Once the cache registers are fully written, a programming operation is initiated to transfer the cached data into the FLASH storage area. After the programming operation for one group is initiated, the FLASH control unit proceeds to the other group, where the process of cache writing and programming is sequentially repeated.

As illustrated in Figure 8, while one group of chips is being programmed, data are sequentially written into the data registers of the four planes in the other group. Upon completion of programming in the previous group, the data registers of the four planes will have been fully written. This allows the current group to commence programming. The alternating process between Group 1 and Group 2 effectively conceals the programming overhead. A shared 128 bit-wide data bus is utilized by both groups. The memory rate is doubled by the addition of a chip select signal. A maximum data rate of 11.98 Gbps is achieved by the proposed storage architecture.

3. Verification and Analysis

The S-SSR system was implemented on the Xilinx XC7K325TFFG900-2 [28], which features 203,800 LUTs, 407,600 flip-flops, and 19.16 Mb of BRAM. Validation and analysis will be conducted with a focus on two aspects: the resilience of the system against bit upset and its overall performance.

3.1. Resilience to Bit Upset

Bit upset can occur in two forms, SBU and MBU. The frequency of SBU is significantly higher than that of MBU. RS encoding is applied to effectively prevent data errors caused by SBU. The circumstances surrounding MBU are more complex. Various flip patterns can occur under different radiation intensities, as illustrated in Figure 9 [29,30,31]. Patterns a to c in the figure are identified as double-bit upset (DBU). Patterns d to f are categorized as triple-bit upset (TBU). Patterns g to k are designated as quadruple-bit upset (QDBU). Pattern l is classified as a quintuple-bit upset (QTBU). The figure enumerates potential upset patterns. Other patterns have been empirically shown to have a negligible occurrence probability.

The interleaved coding method used in this study ensures that the distance between two adjacent symbols within the same error correction sequence is at least three symbols. If any of the specified patterns occur, the erroneous symbols are distributed across different sequences. Each sequence experiences at most one symbol error. This situation remains within the error tolerance of the error correction, allowing for successful correction. To validate the system resilience against bit flips, an error injection method was utilized. A set of correct data was generated and written to FLASH memory. Errors were injected into the memory using external debugging techniques. The data were then read and corrected. A comparison was made between the read data and the original written data. If the data matched, it was concluded that the proposed system effectively mitigates this type of error. Experimental validation demonstrated that errors associated with all the aforementioned patterns can be corrected. This confirms the system effectiveness against both single-bit and multi-bit upsets.

To emphasize the resistance of the proposed system to particle-induced bit flips and its encoding efficiency, a comparison was performed with schemes proposed in recent years. The evaluation was conducted in three aspects: operating frequency, throughput, and radiation resistance. The system encoding efficiency was assessed through operating frequency and throughput. The system radiation resistance was measured based on the types of bit flips that can be withstood. The detailed results are presented in Table 1.

The proposed system achieves an operating frequency that is 3.2 to 4 times higher than those of other schemes. Its throughput is increased by 5.52 to 21 times, and the highest level of radiation resistance is attained. In [32,33], only a Hamming code-based approach is employed, resulting in limited radiation resistance. In [13], a combination of RS codes and LDPC codes [36] is used, but only DBU events with the pattern shown in pattern a can be prevented. In [34], two distinct radiation resistance strategies are applied based on the criticality of data. Most data are protected only against SBU events, while a limited portion of critical data is safeguarded against MBU events. In [35], data from the same parity sequence are distributed across different storage regions, effectively preventing all DBU events. In [9], an iterative interleaving approach based on LDPC coding is introduced, significantly enhancing radiation resistance. However, excessive resource consumption and low throughput are caused by the computational complexity and iterative processes. In the proposed system, a lightweight error detection and correction method is adopted. This method is combined with pipelining techniques to achieve significant improvements in operating frequency and throughput. Furthermore, an efficient interleaving method is employed to enhance the system radiation resistance.

3.2. Performance

The resource utilization of the proposed system is shown in Table 2. The table lists the resource usage for each sub-unit. The entry labeled “Proposed System” represents the FPGA resources used for data processing. This excludes the resources occupied by the storage unit FPGA. In total, the system utilizes 34.62% of Slice LUTs, 15.82% of Slice Registers, and 17.52% of Block RAM. The system has sufficient resource margins, ensuring accurate timing. This allows each component to operate reliably under the specified clock frequencies.

Throughput is a key performance metric for the S-SSR system. Before data are stored, it must be organized into predefined packets. These packets typically include fields such as the header, packet count, satellite time code, sensor identifier, and packet checksum. The total packet size is 2048 bytes, with 2036 bytes dedicated to the actual data. This gives a transmission efficiency of 99.414% (calculated as 2036/2048). Once 4 bytes of ECC check bits are added to each 252-byte data block, the transmission efficiency drops slightly to 98.4375% (calculated as 252/256). Considering the overhead from data packetization and ECC checks, the maximum average data reception rate for a single storage unit is 11.7237 Gbps. For the entire system, the maximum rate is 46.8948 Gbps. If the payload average transmission rate exceeds this threshold, data overwrite errors will occur in the SSR. A comparison in Table 3 shows the average data rates of several SSR systems, demonstrating the exceptionally high throughput achieved by the proposed system. To further verify whether the system can maintain its performance under the extreme temperature conditions of space, the system was placed in a temperature-controlled chamber to conduct high- and low-temperature storage tests. The low-temperature condition was set at −25 °C, while the high-temperature condition was set at +60 °C. Once the ambient temperature reached the preset conditions and stabilized, the device was activated to receive data at the rated speed. After data reception was completed, the data were read and verified for integrity using their error-checking codes. The experimental results demonstrate that the system was able to correctly receive and store data under both extreme low- and high-temperature conditions. Furthermore, the reception rate achieved the maximum value specified by the system.

4. Conclusions

The novel architecture of the high-speed S-SSR developed in this study effectively addresses the limitations posed by current storage systems in the context of electromagnetic spectrum sensing for space applications. The primary challenges, such as the limited throughput of error correction algorithms, restricted I/O pins of FPGAs, and inefficiencies in FLASH control, have been overcome through a combination of innovative techniques. The introduction of the 10-stage pipelined RS(256,252) encoder significantly boosts the system error correction efficiency. By employing a distributed storage approach, where multiple FPGAs control independent storage areas, the design efficiently handles the parallel expansion of FLASH chips, thereby overcoming the I/O pin limitation. Another key innovation is the optimization of the FLASH control unit, achieved through multi-plane and cache operations, which dramatically improves data storage speeds without requiring additional I/O pins. By using a four-stage pipeline in conjunction with interleaved operations, the system is capable of efficiently managing data transfers between the cache and storage cells, further enhancing overall performance. Additionally, the proposed system effectively addresses both SBU and MBU through the use of RS encoding and an interleaved coding method. By ensuring a minimum distance of three symbols between adjacent symbols in the same error correction sequence, the system distributes errors caused by common MBU patterns across different sequences, keeping errors within the correction capacity of the RS algorithm.

The architecture was thoroughly evaluated on the Xilinx XC7K325T platform, with a focus on throughput, error correction capability, and system stability. The system capability to correct all categorized error patterns was confirmed through analysis and validation, demonstrating its resilience against both SBU and MBU events. The results demonstrate that the proposed S-SSR can handle high data rates and correct errors effectively, offering superior performance compared to existing systems. The throughput achieved by the system is notably higher than other state-of-the-art solutions, making it well-suited for future deployment in high-demand space exploration missions, where reliable and high-capacity data storage is essential.

In conclusion, this study presents a robust, high-throughput S-SSR architecture that not only addresses the limitations of current designs but also provides a scalable and reliable solution for spaceborne data storage. The advancements in error correction, data throughput, and radiation resistance ensure that the proposed system will play a vital role in future space missions, particularly those involving complex electromagnetic spectrum sensing tasks.

Author Contributions

Software, X.L.; Validation, X.L.; Formal analysis, X.L.; Investigation, X.L.; Writing—original draft, X.L.; Writing—review & editing, X.L. and L.Z.; Supervision, L.Z.; Project administration, X.L.; Funding acquisition, Y.Z. All authors have read and agreed to the published version of the manuscript.

Data Availability Statement

The original contributions presented in the study are included in the article, further inquiries can be directed to the corresponding author.

Conflicts of Interest

The authors declare no conflicts of interest.

Footnotes

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Figures and Tables

Figure 1. System architecture of the high-speed S-SSR. This diagram presents the integrated setup of the S-SSR, showcasing the distribution of data management across multiple FPGAs.

Figure 2. Implementation of the RS(256,252) algorithm in a cyclic XOR architecture. This operational flowchart illustrates the detailed computational process of the algorithm from start to end.

Figure 3. Detailed view of the 10-stage pipeline structure of the RS(256252) algorithm. This figure illustrates the implementation of the algorithm from Figure 2 in a pipelined architecture. The relevant code for this module has been open-sourced from Github (https://github.com/lixuf/ECC_array/tree/main (accessed on 1 January 2024)).

Figure 4. Timing diagram illustrating the processing and output of RS(256252) error control module.

Figure 5. Implementation of interleaving unit. This figure demonstrates how the four interleaving methods are output in a pipelined manner using multiplexers.

Figure 6. Example of resilience against bit-upset. This figure provides an example of how various bit-upset events are distributed across multiple error-correction sequences.

Figure 7. Detailed view of the storage area implementation: In the figure, the data lines are shared between two groups of chips, while the control lines are used independently by each group.

Figure 8. Illustration showing the data programming process between two groups of FLASH chips with concealed overhead.

Figure 9. Patterns of bit upset events, including double-bit, triple-bit, quadruple-bit, and quintuple-bit upsets. (a–c) Patterns of double-bit upsets. (d–f) Patterns of triple-bit upsets. (g–k) Patterns of quadruple-bit upsets. (l) Pattern of quintuple-bit upsets.

Table 1

The comparison between the existing systems and our proposed system.

Design	Frequency	Throughput	Radiation Resistance	Year
[32]	100 MHz	5.12 Gbps	All SBU	2017
[13]	100 MHz	6.74 Gbps	All SBU & Limited DBU	2017
[33]	120 MHz	2.79 Gbps	All SBU	2018
[34]	100 MHz	2.40 Gbps	All SBU & Limited MBU	2020
[35]	125 MHz	6.40 Gbps	All SBU & All DBU	2021
[9]	100 MHz	9.12 Gbps	All SBU & Most MBU	2024
Proposed	400 MHz	49.624 Gbps	All SBU & Most MBU	2024

Table 2

FPGA resource utilization for the proposed system: The percentages in parentheses represent the proportion of each resource utilized relative to the total available resources on the chip.

Name	ECC Array	Interleave Unit	Data Distribution Unit	Proposed System
Slice LUTs	2060 (1.01%)	585 (0.29%)	410 (0.21%)	70,566 (34.62%)
LUT as Memory	412 (0.64%)	0	0	6081 (9.50%)
LUT as Logic	1648 (0.81%)	585 (0.29%)	410 (0.21%)	64,485 (31.64%)
Slice Registers	4349 (1.07%)	1552 (0.38%)	1242 (0.31%)	49,147 (12.06%)
Block RAM	0	0	0	78 (17.52%)
DSP	0	0	0	0
F7 Muxes	0	0	0	149 (0.15%)
F8 Muxes	0	0	0	3 (0.05%)

Table 3

Comparison of capacity and throughput across several SSR systems [13,37,38,39,40].

Mission	Type	Capacity	Throughput	Year
SJ-5	SDRAM	512 Mb	1 Mbps	1999
Double Star	SDRAM	2 Gb	800 Kbps	2003
Chang’e 1	SDRAM	48 Gb	2 Mbps	2007
Chang’e 2	NAND Flash	128 Gb	500 Mbps	2010
GF-1	NAND Flash	1 Tb	-	2013
Landsat-8	NAND Flash	4 Tb	-	2013
GF-2	NAND Flash	4.9 Tb	-	2014
TJS-7	NAND Flash	128 Tb	-	2014
DAMPE	NAND Flash	128 Gb	492 Mbps	2015
Sentinel-2	NAND Flash	2.4 Tb	1 Gbps	2015
SJ-10	NAND Flash	256 Gb	512 Mbps	2016
WorldView-4	NAND Flash	3.2 Tb	1 Gbps	2016
SEOSat-Earth	NAND Flash	512 Gb	500 Mbps	2017
CX-3A	NAND Flash	512 Gb	558 Mbps	2018
KhalifaSat	SDRAM	512 Gb	320 Mbps	2018
NovaSAR-1	NAND Flash	4.3 Tb	500 Mbps	2018
PRISMA	NAND Flash	256 Gb	600 Mbps	2019
Sentinel-6	NAND Flash	352 Gb	500 Mbps	2020
MicroCarb	NAND Flash	800 Gb	800 Mbps	2020
CASEarth	NAND Flash	8 Tb	2.6 Gbps	2021
ASO-S	NAND Flash	4 Tb	800 Mbps	2022
Sentinel-5	NAND Flash	600 Gb	800 Mbps	2024
Proposed	NAND Flash	16 Tb	46.8948 Gbps	2024

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