Multi-functional polymorphic memory based on 2D ferroelectric tunnel junctions

Abstract

In modern data-intensive applications, the segmentation of memory and processors leads to reduced throughput, lower energy efficiency, and increased latency. Functional memory systems address this by enabling operations beyond basic read-write tasks within memory arrays, as in in-memory computing (IMC). Non-volatile memories further enhance efficiency by storing data without static power loss. Of particular interest are 2D ferroelectric tunnel junctions (FTJs), such as those based on MoS₂, due to their compact size, high ON–OFF ratios, and CMOS compatibility. In this work, we propose a novel memory design using MoS₂-based FTJs that reliably store data via ferroelectric polarization and support multiple in-memory functions. These include Boolean logic, batch reads, variation-robust self-referencing reads, and reconfigurable content-addressable memory functionality through peripheral circuit changes. We validate these polymorphic behaviors through measured characteristics of fabricated 2D MoS₂-FTJs and simulations using the GlobalFoundries’ 22 nm silicon-on-insulator technology node.

Introduction

Modern data-intensive applications, such as machine learning, artificial intelligence, and large-scale simulations, face energy, latency, and throughput bottlenecks due to the physical segmentation of memory and processing units-a challenge commonly referred to as the memory wall bottleneck¹. This issue is further exacerbated by continued technology scaling, where shrinking process dimensions lead to higher interconnect resistance due to thinner metal wires and increased coupling capacitance between adjacent interconnects^2,3. A promising approach to overcoming these challenges is to create functional memory systems that can perform computations beyond simple read-write memory operations. Among such functional operations is in-memory computing (IMC), which integrates computation directly within memory, reducing the need for frequent data transfers. By processing data where it is stored, IMC enhances both speed and energy efficiency, effectively mitigating the fundamental limitations of conventional von Neumann architectures^{4, 5, 6–7}.

Given its potential to address these challenges, IMC has attracted significant research interest, leading to various approaches that range from conventional CMOS technology to emerging beyond-CMOS solutions. In particular, non-volatile memory (NVM) has become a cornerstone of in-memory computing (IMC), a system designed to overcome the von Neumann bottleneck by performing computations directly within memory arrays⁸. Among the various NVM-based IMC solutions, 2D materials have been widely explored, each offering distinct advantages as reported in refs. ^9,10. For instance, spintronic devices leverage on electron spin to accomplish non-volatile, low-power, high-endurance (≈10⁵ cycles), and scalable memory and computing applications, as reported in^{11, 12, 13, 14–15}. Recent research shows that spin-transfer torque magnetic random-access memory (STT-MRAM) arrays are efficient for in-memory binary neural network (BNN) computation^16,17. These implementations transform the multiply-and-accumulate (MAC) operation into efficient XNOR and accumulation operations performed directly within the memory arrays, significantly reducing hardware complexity and power consumption. High parallelism is achieved through simultaneous multi-wordline activation, substantially enhancing computing speed and energy efficiency.

Also, researchers in refs. ^{18, 19–20} reported that resistive switching devices are promising for neuromorphic computing, memory applications, and in-memory logic operation, offering advantages such as non-volatility, high scalability, low power consumption, and high performance. Recent studies have demonstrated in-memory logic architectures using resistive random-access memory (ReRAM)^18,20,21. investigated a TiN/TiO_X-based Computational Random-Access Memory (CRAM) structure capable of performing logic functions such as AND, NAND, and NOR directly within memory arrays, exhibiting great energy efficiency and showing promise for full adder operations when optimized.²² presented the SIMPLY architecture, which integrates IMPLY logic with ReRAM in a 1T–1R configuration, giving better reliability and energy efficiency compared to CMOS, particularly when accounting for the von Neumann bottleneck. These developments highlight ReRAM’s potential as a key enabler for next-generation in-memory computing systems, which demand both compactness and ultra-low power consumption.

Phase-change memory (PCM), another promising candidate among emerging memory technologies, offers scalability and multi-level storage capabilities. However, its adoption is hindered by relatively slow write speeds (on the order of microseconds) and high power consumption during phase transitions, which lessen overall efficiency^23,24. In recent times, researchers have explored in-memory computing using PCM-based design. For example, the design in ref. ²⁵ introduces the Pinatubo architecture, which performs bitwise logic operations (e.g., AND, OR, XOR) directly within memory arrays, enabling parallel computation across multiple rows. Another work by Hoffer et al.²⁶ implements stateful logic gates (NOR, OR, IMPLY, NIMP) using PCM cells configured in a crossbar array, allowing single-step logic execution without data movement. Collectively, these designs highlight the potential of PCM for energy-efficient, high-throughput processing-in-memory (PIM), despite its intrinsic switching limitations.

In contrast, 2D ferroelectric materials are a viable approach for designing multifunctional devices as a result of their spontaneous polarization that can be switched using an external electric field. This polarization reversal generates different resistance states, which are utilized in NVM-IMC, and biological synapses^{27, 28–29}. The three main categories of 2D non-volatile ferroelectric memory are ferroelectric RAM (FeRAM), ferroelectric tunnel junction (FTJ), and ferroelectric field-effect transistor (FeFET)³⁰. While FeFETs typically show higher ON current and faster access time, they often suffer from limited ON/OFF ratio due to charge trapping and read disturbances³¹. FeRAMs are known for endurance and fast switching, but their three-dimensional scalability and bitcell area are constrained by the 1T–1C configuration³². In contrast, recent advancements place FTJs as a standout candidate for next-generation IMC systems. Studies show FTJs achieving sub-nanosecond switching and femtojoule-level energy efficiency, far surpassing other NVMs, making them ideal for AI and machine learning applications where rapid data access and minimal power are critical^{33, 34–35}. Unlike conventional FeRAM, ferroelectric tunnel junctions (FTJs) leverage the high tunneling electro resistance (TER), which ranges from 10³ to 10⁶, to enable non-destructive readout, significantly improving energy efficiency and lowering the need for high write voltages, in addition to its CMOS compatibility. Building on these advantages, recent studies have shown that 2D FTJs further extend the benefits of conventional FTJ technology. These devices exhibit excellent scalability, low-power operation, and support for multi-level resistive states-key features for neuromorphic computing. Demonstrations of 2D ferroelectric-based memory and synaptic device architectures highlight their potential in in-memory computing and seamless integration with CMOS platforms³⁶. Additionally, flexible BiFeO₃-based ferroelectric memristors have been shown to achieve stable resistive switching and high pattern recognition accuracy, pointing to strong suitability for edge AI and wearable applications³⁷. Together, these features position FTJs-particularly in their 2D implementations-as a compelling option for future nonvolatile memory and neuromorphic computing systems. Their ability to deliver low power consumption, fast switching, and high functional density paves the way for energy-efficient, high-performance computing architectures^{38, 39–40}. In this work, we present a multifunctional polymorphic memory that uses the ferroelectric polarization states of FTJs based on MoS₂ and the associated high ON–OFF ratio, allowing multiple functionalities through modulation of the peripheral circuit alone. The presented versatile memory not only provides non-volatile data storage but also supports in-memory Boolean computation, novel batch read operations, self-referencing for variation-resilient reads, and can be reconfigured as a content-addressable memory.

The key contributions of this work are as follows:

• We propose a multi-functional polymorphic memory, designed using MoS₂-based ferroelectric tunnel junctions (FTJs), which retains stored data in a non-volatile manner, enables reliable data writing, and supports variation-robust, disturb-free read operations.

• The proposed memory supports multiple functional operations, including (i) Boolean in-memory computations—multi-bit NOR and NAND operations on stored data, (ii) novel batch read operations, (iii) variation-robust self-referencing memory read operations, and (iv) can be configured as a content-addressable memory (CAM) for highly parallel search operations. Notably, all these functionalities are enabled solely through reconfiguration of the peripheral circuits while the 2D FTJ-based memory array remains intact.

• We designed and validated multi-functional operations by leveraging the measured characteristics of fabricated MoS₂-FTJ devices exhibiting excellent ON–OFF ratio, along with simulated CMOS transistors in commercial GlobalFoundries’ 22 nm FD-SOI technology node.

Results

In this section, we will discuss our fabricated 2D material-based ferroelectric tunnel junction (FTJ) stack, including its operating principle and measured resistance characteristics. Additionally, we will present the multi-functional bitcell design based on the FTJ stack, outlining its read and write operations. Furthermore, we will cover the additional functionalities of our proposed design, such as in-memory Boolean operations (NOR, NAND, and XOR), batch read operation, self-referencing for variation-robust read operation, and a content-addressable memory (CAM) configuration, all utilizing the same bitcell.

2D material-based FTJ device structure and resistance vs voltage characteristics

Two-dimensional (2D) ferroelectric tunnel junctions (FTJs) offer significant advantages for modern computing needs. The reduced dimensionality and unique electronic properties of 2D materials enable ferroelectric switching at comparatively lower voltages^41,42 compatible with the typical CMOS supply voltages while offering a high ON-OFF ratio. For instance, studies have demonstrated that devices utilizing 2D ferroelectric materials can achieve polarization switching within 1.2 V applied electric fields⁴³, thereby reducing power consumption and enhancing device efficiency. For our design, we chose 3R MoS₂ as our tunneling channel. The switching mechanism of the bilayer 3R MoS₂ is primarily attributed to interlayer sliding. In the 3R stacking configuration, each MoS₂ layer is slightly displaced relative to the adjacent one, resulting in a non-centrosymmetric structure that exhibits spontaneous out-of-plane polarization⁴⁴. Applying an external electric field can induce a relative lateral shift between the two layers, effectively switching the stacking order from an AB to a BA configuration^45,46, as Fig. 1b shows. This interlayer displacement alters the polarization direction, enabling ferroelectric switching. Such sliding-driven ferroelectricity in van der Waals materials offers a novel approach to achieving non-volatile memory functionalities. For a typical 3R MoS₂ FTJ, we achieved both low switching voltage and high ON–OFF ratios, as required to realize the proposed memory applications.

Fig. 1 3R MoS₂-based 2D FTJ device. [Images not available. See PDF.]

a Structure of 3R MoS₂-based 2D FTJ device. The 3R MoS₂ is the ferroelectric tunneling layer, with graphene and Au as top and bottom contacts. b The spontaneous polarization of the MoS₂ FTJ. The black arrow indicates the polarization direction. Left: Polarization direction in FTJ device. Right: Corresponding stacking of the bilayer 3R MoS₂ layer. c Representative I–V characteristics curve obtained from the FTJ device. The arrows indicate the sweeping directions. d Resistance behavior characteristics curve obtained from the FTJ device. The arrows indicate the sweeping directions. The read voltage V_READ = 1 V.

The fabricated ferroelectric tunnel junction (FTJ) device comprises a layered structure of Graphene/bilayer 3R- MoS₂/Au, as Fig. 1a shows. In this configuration, graphene serves as the top electrode, bilayer 3R-phase molybdenum disulfide (MoS₂) as the ferroelectric active layer, and gold (Au) as the bottom electrode. The thickness of the MoS₂ layer is strictly chosen to be a bilayer to maintain switchable polarization under low switching voltage. To evaluate the performance of the FTJ device, current–voltage (I–V) characteristics were measured by sweeping the voltage from −1.5 V to +1.5 V, as depicted in Fig. 1c. The I–V curve exhibits a pronounced hysteresis loop, with a switching voltage of around 1.5 V, indicating the transition between AB and BA stacking and their associated high-resistance and low-resistance states. Further investigation into switching behavior between the high-resistance and low-resistance state in such FTJ, we study the resistance–voltage behavior in this FTJ device. Shown in Fig. 1d, the resulting plot of voltage versus resistance reveals distinct resistance switching events occurring at approximately ±1.5 V, signifying the device’s ability to toggle between high-resistance and low-resistance states. When read at V_READ = 1 V, the figure shows that the on/off resistance ratio of this FTJ exceeds 10³. Multiple devices with the same structure were made to verify the performance of this FTJ device. The on/off ratios are commonly over 10³, and some can even reach 10⁴, underscoring the device’s potential for high-performance non-volatile memory applications.

Proposed multi-functional polymorphic memory design and operation

Figure 2a illustrates the proposed polymorphic bitcell, which utilizes a MoS₂-based ferroelectric tunnel junction (FTJ) as described in Section “2D material-based FTJ device structure and resistance vs voltage characteristics”. The bitcell consists of two ferroelectric tunnel junctions (FTJs) and a pair of access transistors, facilitating both read and write operations. It adopts a 2T–2R architecture, where the two MoS₂-based FTJs–FTJ1 (top FTJ) and FTJ2 (bottom FTJ), as illustrated in Fig. 2a, are connected in series between the top and bottom source lines, SL_T and SL_B, respectively. The Au electrode of FTJ1 is linked to the top source line SL_T, while the Graphene electrode of FTJ2 connects to the bottom source line SL_B. The intermediate node, where the two FTJs are connected in series, serves as the storage node, denoted as Q in the figure. M₁ represents the read access transistor, with its gate connected to the storage node, its drain linked to the read word line (RWL), and its source connected to the read bitline (RBL). M₂ denotes the write access transistor, which is controlled by the write word line (WWL) and connects the write bitline (WBL) to the storage node Q.

Figure 2b shows the circuit model for the proposed bitcell. The FTJ can be represented as a resistor, with FTJ1 and FTJ2 modeled as resistors R₁ and R₂, respectively. The resistance values are determined by the ferroelectric polarization states of the FTJs, as explained in Section “2D material-based FTJ device structure and resistance vs voltage characteristics”. In this bitcell, logic-0 is encoded when R₁ = R_H (high-resistance or off-resistance state), where the ferroelectric polarization is oriented from Au to Graphene, and R₂ = R_L (low-resistance or on-resistance state), where the polarization is directed from Graphene to Au. Conversely, logic-1 is encoded when R₁ = R_L and R₂ = R_H. Figure 2c presents a 2 × 2 array configuration of our proposed FTJ-based polymorphic bitcell. Note that source lines (SL_T and SL_B) are shared across rows, wordlines (RWL and WWL) are shared across rows, and bitlines (RBL and WBL) are shared across columns. Additionally, the source lines can be connected to either VDD or GND depending on the specific memory or functional operation, which will be further discussed in subsequent sections. The non-volatile nature of the FTJ allows the designed bitcell to store data (resistance states) by maintaining the polarization state without requiring a constant power supply.

Fig. 2 Proposed polymorphic bitcell design, hardware model, and array configuration. [Images not available. See PDF.]

a Schematic of the proposed polymorphic bitcell utilizing a 2D material-based ferroelectric tunnel junction (FTJ), comprising two FTJs and two access transistors for enabling read and write operations. b Circuit model of the proposed bitcell, where each FTJ is modeled as a resistor, with resistance values dependent on its ferroelectric polarization state. c A 2 × 2 array configuration of the proposed FTJ-based polymorphic bitcell, with shared source lines, wordlines, and bitlines across rows and columns.

Figure 3a illustrates the read operation for retrieving logic-0 and logic-1 from a memory array. As an example, consider a 1 × 2 array where the left bitcell stores ‘0’ and the right bitcell stores ‘1’. To initiate the read process, the bottom source line (SL_B) is grounded, while the top source line (SL_T) is supplied with a small read voltage (V_READ). It is important to note that V_READ is set lower than the write voltage to prevent any unintended changes in the ferroelectric polarization states of the FTJs during reading. To avoid disturbances in other bitcells, the source lines of non-selected rows are also connected to GND. Initially, all the read bitlines (RBL) are discharged to GND. The read operation is activated by enabling the read wordline (RWL). If a bitcell, such as ⟨1, 1⟩, stores a ‘0’, the storage node (Q) remains near GND due to the voltage divider formed by R_H and R_L, given that their ON–OFF resistance ratio exceeds 10³. As a result, the read access transistor remains off, preventing conduction, and the bitline (e.g., RBL⟨1⟩) remains close to GND, which is lower than the threshold voltage (V_TH) of the column-parallel sense amplifier, leading to an output of ‘0’. Conversely, if the bitcell (e.g., ⟨1, 2⟩) stores a ‘1’, the storage node (Q) is pulled closer to V_READ due to the reversed voltage divider configuration formed by R_L and R_H. Consequently, the read access transistor turns on, allowing the bitline (e.g., RBL⟨2⟩) to charge up toward V_RWL. Since this voltage exceeds the threshold voltage (V_TH) of the sense amplifier, the output is read as ‘1’.

Fig. 3 Memory array read and write operations. [Images not available. See PDF.]

a Illustration of the read operation in a memory array for retrieving logic-0 and logic-1. b, c Representation of the two-phase write operation, where the ferroelectric polarization states of the FTJs in the selected bitcells are set in two phases. In phase P1, the write “0” operation is applied to the selected bitcells, and in phase P2, the write “1” operation is applied, completing the row write operation. Here, the red lines represent the active lines, while the green lines indicate the disabled or grounded lines.

Figure 3b, c illustrates the two-phase write operation of the memory array, which ensures the correct encoding of logic states by setting the ferroelectric polarization of the FTJs within each bitcell. Writing data to the array requires applying a sufficiently large voltage pulse to the Au or Graphene electrodes, depending on the intended logic state. This process is executed in two distinct phases for a given row. During the first phase (P1), the write wordline (WWL) activates the selected row, and the write ‘0’ operation is initiated. In this phase, the column write driver configures the write bitlines (WBLs) such that only the bitcells intended to store ‘0’ undergo polarization switching, while those meant to store ‘1’ are disabled through specific voltage configurations on their bitlines and source lines. In the second phase (P2), the process is reversed: bitcells previously set to ‘0’ are left disabled, while those designated for ‘1’ undergo polarization flipping, completing the write process for the entire row.

To illustrate this process, consider a 1 × 2 array where the bitcell at ⟨1, 1⟩ needs to be programmed to ‘0’, and the bitcell at ⟨1, 2⟩ needs to be programmed to ‘1’. During phase P1, the write wordline (WWL) of the selected row is activated, and both source lines (SL_T and SL_B) are driven to the write voltage (V_WRITE). The write bitline corresponding to bitcell ⟨1, 1⟩ (WBL⟨1⟩) is set to GND, while WBL⟨2⟩ is set to V_WRITE, ensuring selective polarization switching. In the bitcell ⟨1, 1⟩, a voltage pulse appears across the FTJs, setting the polarization of the top FTJ from Au to Graphene and the bottom FTJ from Graphene to Au. Consequently, these FTJs exhibit high (R_H) and low (R_L) resistance states, respectively, encoding a logic-0 state. Meanwhile, in bitcell ⟨1, 2⟩, the voltage configuration ensures the voltage difference between the FTJ electrodes is zero and thereby prevents any change, ensuring that no unintended polarization switching occurs. Thus, during this phase, only the bitcells that need to store ‘0’ undergo a write operation, while those intended for ‘1’ remain unchanged.

In the second phase (P2), the roles are reversed to complete the write operation for bitcells that need to be written as ‘1’. The source lines (SL_T and SL_B) are set to GND, and the write bitlines are configured according to the data input-GND for logic ‘0’ and V_WRITE for logic ‘1’. As a result, bitcells previously written to ‘0’ remain unaffected since both terminals of their FTJs are grounded. However, for bitcells designated to store ‘1’, a voltage pulse appears across the FTJs, setting the polarization of the top FTJ from Graphene to Au and the bottom FTJ from Au to Graphene. This results in low (R_L) and high (R_H) resistance states, encoding a logic-1 state. The shared source line setup guarantees that all bitcells in the row undergo the two-phase write operation at the same time, enabling efficient and reliable data writing.

Note, the read operation of the proposed bitcell is inherently decoupled, ensuring that the charging current of the read bitline (RBL) does not pass through the FTJs within the memory bitcell. This separation allows the read speed to be optimized by the peripheral row driver circuit without the risk of bitcell flipping, thereby eliminating read-disturb failures. Additionally, the series resistive divider effectively maintains the stored logic state, enhancing the stability of the design. The structure remains resilient against global variations such as process corners, temperature fluctuations, and supply voltage changes, as the voltage ratio remains consistently close to either V_READ or GND due to the high ON–OFF ratio of our fabricated 2D FTJs. This inherent robustness of our proposed structure ensures a variation-tolerant and disturbance-free memory operation.

Figure 4 presents the functional validation of the memory read operation. This verification is conducted using GlobalFoundries’ 22 nm FD-SOI technology node while incorporating a 3-sigma process variation analysis over 1000 samples to account for local mismatches in the driver, sense amplifier, and access transistors. The driver activates the wordline and source lines, enabling the read operation. The sense amplifier, connected to the read bitline, compares the bitline voltage against a predefined threshold. If the bitline voltage exceeds the threshold, the sense amplifier outputs ‘1’; otherwise, it outputs ‘0’. In this simulation, RBL1 is connected to a memory cell storing ‘0’, while RBL2 is linked to a memory cell storing ‘1’. Upon activation of the read wordline (RWL), the behavior of the bitcell is determined by the stored data. If the bitcell holds ‘0’, as in the case of RBL1, no charging occurs, and its voltage remains near GND, staying below the sense amplifier’s threshold voltage (V_TH). The bottom subplot confirms that, across all 1000 samples, the output (OUT1) remains consistently ‘0’ when the sense amplifier is activated (SEN = VDD). Conversely, when RBL2 is connected to a bitcell storing ‘1’, the bitline experiences charging upon RWL activation. Once the sense amplifier is triggered, the voltage on RBL2 surpasses V_TH in all 1000 cases, ensuring a reliable readout (OUT2) of ‘1’. This analysis confirms the robustness of the memory read operation under process variations. Note, the write operation simply results in either application of voltage greater than the write voltage across FTJs that need to be switched, while FTJs that do not need switching see zero voltage difference across their top and bottom electrodes. This switching behavior is exactly the same as the switching behavior depicted in device characterization of Fig. 1(c) and hence has not been repeated here.

Fig. 4 Functional validation of memory read operation under process variations. [Images not available. See PDF.]

Here, RWL and SEN denote the read wordline and sense amplifier activation signal, respectively. RBL1 and RBL2 correspond to bitlines connected to bitcells storing ‘0’ and ‘1’, respectively. OUT1 and OUT2 represent the outputs from the sense amplifier.

In-memory computing

Our proposed FTJ bitcell enables multi-bit in-memory Boolean computation of NOR and NAND logic by simultaneously activating multiple wordlines within the memory array. Figure 5a, b illustrates the in-memory NOR and NAND operations for all possible input combinations. For discussion, a 2 × 1 bitcell array is shown, where the read wordlines (RWL⟨1⟩ and RWL⟨2⟩) are activated simultaneously to perform Boolean logic operations between stored words. The stored node voltages, Q1 and Q2, depend on the resistance states of the two FTJs inside each bitcell. NOR and NAND operations are enabled using the same bitcell array by applying the read voltage to either the top source line (SL_T) or the bottom source line (SL_B), while keeping the other grounded, respectively. The bitcells across multiple rows share a common column line, and a sense amplifier at the periphery compares the read bitline voltage (RBL) against a threshold to determine the output logic (Y). Since the sense amplifier is a differential circuit that generates both the output and its complement, we leverage the complementary output for the NOR operation and the non-complementary version for the NAND operation.

Fig. 5 In-Memory Boolean computation using FTJ bitcells. [Images not available. See PDF.]

a NOR and b NAND operations. Here, the activated read access transistors are highlighted in red, while the off access transistors are indicated in green.

In a NOR operation, the logic output is ‘1’ only when all inputs are ‘0’. If any input is ‘1’, the NOR output becomes ‘0’. To implement this operation, the top source line (SL_T) is activated with the read voltage (V_READ), while the bottom source line (SL_B) is set to GND. Both wordlines are simultaneously activated to perform the NOR operation between two words. When Q1 = 0 and Q2 = 0, the read access transistors remain OFF due to the resistance states (R₁ = R_H and R₂ = R_L) of the bitcells. Consequently, the read bitline (RBL) does not experience any charging, keeping its voltage below the threshold voltage (V_TH) of the sense amplifier. As a result, the complementary output of the sense amplifier is ‘1’. However, when any of the inputs (e.g., 01, 10, or 11) is ‘1’, at least one read access transistor is activated. This causes charging on RBL, raising its voltage above the threshold of the sense amplifier. Consequently, the complementary output of the sense amplifier transitions to ‘0’.

In a NAND operation, the output is ‘0’ only when all inputs are ‘1’. If at least one input is ‘0’, the NAND output is ‘1’. To execute this operation, the bottom source line (SL_B) is supplied with the read voltage (V_READ), while the top source line (SL_T) is grounded. Both wordlines are activated simultaneously to perform the NAND operation across two words. When both bitcells store ‘1’ (i.e., Q1 = 1 and Q2 = 1), the resistance states (R₁ = R_L and R₂ = R_H) of the bitcells prevent the read access transistors from turning ON. As a result, the read bitline (RBL) remains uncharged, keeping its voltage below the sense amplifier’s threshold voltage (V_TH), leading to an output of 0’. Conversely, if any input (e.g., 00, 01, or 10) is ‘0’, at least one read access transistor is switched ON. This allows RBL to charge, increasing its voltage beyond the sense amplifier’s threshold. Consequently, the sense amplifier produces an output of ‘1’. Although the figure illustrates Boolean NOR and NAND operations between two words, n-bit Boolean NOR and NAND operations can be performed by simultaneously activating the ‘n’ read wordlines, with the operating principle remaining the same.

Figure 6 demonstrates the Boolean in-memory NOR operation for all possible input combinations between two bitcells. A total of 1000 Monte Carlo simulations were conducted to validate the functionality of the in-memory NOR operation using our proposed FTJ bitcells. The figure shows that for input combinations ‘01’, ‘10’, and ‘11’, the read bitline voltage (RBL) exceeds the threshold voltage (V_TH) of the sense amplifier, causing the complementary output to be ‘0’. Conversely, for the ‘00’ case, the RBL remains below V_TH, resulting in an output of ‘1’. This confirms the correct operation of the NOR logic. Note that the NAND logic operates symmetrically, with the difference being in the source line voltages, and the output is checked from the non-inverting sense amplifier node.

Fig. 6 Functional validation of the in-memory Boolean NOR operation considering process variations. [Images not available. See PDF.]

In this setup, RWL and SEN represent the read wordline and the sense amplifier activation signal, respectively. RBL refers to the bitline connecting two bitcells from different rows, while OUT indicates the complementary output node from the sense amplifier to enable NOR output.

Batch read operation

The proposed FTJ bitcell array facilitates batch reading of both ‘0’ and ‘1’ values by simultaneously activating multiple rows, making it ideal for enhancing computational efficiency, especially in sparse, data-centric applications. Figure 7a, b demonstrate the n-bit batch read operation for ‘0’, while Fig. 7c, d illustrates the n-bit batch read operation for ‘1’. The operation follows principles similar to in-memory Boolean NOR and NAND operations, respectively. For the n-bit batch read of ‘0’, multiple rows are activated by energizing the RWLs and applying the read voltage (V_READ) to the top source lines (SL_Ts). When all stored data are ‘0’, none of the access transistors are activated, resulting in a read bitline voltage lower than the threshold voltage of the sense amplifier. As a result, the sense amplifier outputs ‘0’, indicating that all bitcells are storing ‘0’ (as shown in Fig. 7a). In contrast, if any bitcell stores ‘1’, the corresponding access transistor will be activated, causing the read bitline voltage to exceed the threshold voltage of the sense amplifier. Consequently, the sense amplifier will output ‘1’, signaling that at least one of the bitcells is storing ‘1’ (as shown in Fig. 7b).

Fig. 7 n-bit batch read operations using the proposed FTJ bitcell array. [Images not available. See PDF.]

a n-bit read of ‘0’ when all selected bitcells store ‘0’, outputting ‘0’. b n-bit read of ‘0’ when at least one bitcell stores ‘1’, outputting ‘1’. c n-bit read of ‘1’ when all selected bitcells store ‘1’, outputting ‘0’. d n-bit read of ‘1’ when at least one bitcell stores ‘0’, outputting ‘1’. Activated read access transistors are shown in red; inactive ones in green.

Similar to the Boolean NAND operation, to perform an n-bit batch read of ‘1’, multiple wordlines are activated, and the read voltage (V_READ) is applied to the bottom source lines (SL_Bs). If all the selected bitcells store ‘1’, none of the access transistors will be activated, causing the read bitline (RBL) to remain below the threshold voltage (V_TH), and the sense amplifier will output ‘0’, indicating that all the bitcells store ‘1’ (as shown in Fig. 7c). However, if any of the bitcells store ‘0’, the corresponding access transistor will activate, charging the read bitline and raising its voltage above the threshold, causing the sense amplifier to output ‘1’ (as shown in Fig. 7(d)).

Figure 8 demonstrates the validation of the n-bit batch read operation for detecting ‘0’ in a single cycle by simultaneously activating multiple wordlines. In this verification, we activate eight bitcells at once to determine whether all store ‘0’. Two test scenarios are simulated: one where all eight bitcells store ‘0’, and another where a single bitcell stores ‘1’ while the remaining seven store ‘0’. A total of 1000 Monte Carlo simulations were performed for each scenario to ensure robustness and validate the operation. In the first scenario (‘00000000’), the figure shows that the read bitline voltage (RBL) remains below the threshold voltage (V_TH) since none of the access transistors are activated, resulting in a sense amplifier output of ‘0’. Conversely, in the second scenario, where one bitcell stores ‘1’, the activation of its corresponding access transistor raises the RBL voltage above V_TH, causing the sense amplifier to output ‘1’. Note that the n-bit batch read operation for detecting all ‘1’ follows a symmetric approach by adjusting the source line voltages (SL_Ts = GND and SL_Bs = V_READ). In this case, a sense amplifier output of ‘0’ signifies that all bitcells store ‘1’ (Fig. 9).

Fig. 8 [Images not available. See PDF.]

Functional verification of the n-bit batch read operation for detecting ‘0’s under process variations, where RWL and SEN denote the read wordline and sense amplifier activation signal, RBL represents the bitline connecting eight bitcells across different rows, and OUT is the sense amplifier output, which is ‘0’ if all bitcells store ‘0’, and ‘1’ if any bitcell stores ‘1’.

Fig. 9 Schematic of the self-referencing circuit for data readout. [Images not available. See PDF.]

The circuit uses two holding capacitors (C_H1 and C_H2) and three control switches (S₁–S₃). In phase Φ₁, charge is stored on C_H1 and in phase Φ₂, C_H2 holds complementary charge. In phase Φ₃, charge sharing occurs between these capacitors, resulting in an average voltage used as the threshold for the sense amplifier to enable variation-resistant self-referencing read operation.

Batch read operations could potentially lead to higher read speed for data-intensive applications. Typically, in a memory array, only one row is read at a time. As shown, our proposed batch read allows reading multiple rows, simultaneously, provided that data shows strong sparsity (i.e., many 0’s or conversely many 1’s). Note, such scenarios frequently arise in machine learning and image processing applications. In such cases, proposed batch read operations can be performed, and sequential row-by-row reads are needed only when batch read detects at least one non-0 or non-1 data in the batch being read.

Self-referencing sensing

The proposed bitcell employs a resistive divider voltage node for data storage, allowing it to generate a dynamic reference voltage while row driver circuits control the source line terminals. This reference voltage acts as a threshold for the sense amplifier, ensuring a robust and variation-resistant read operation. By incorporating column-parallel passive capacitors, the FTJ-based bitcell enables a bitcell-specific self-referencing read mechanism that improves tolerance to local mismatches. The self-referencing read process operates in three cycles: the first two cycles estimate the reference voltage, and the third cycle executes the readout, utilizing the reference to enhance accuracy and reliability.

The self-referencing circuit is composed of two holding capacitors (C_H1 and C_H2) and three control switches (S₁–S₃). In the first phase (Φ₁), switch S₁ is activated along with the read wordline (RWL) and the top source line (SL_T), while the bottom source line (SL_B) is set to GND. This activation allows the selected row to store charge on capacitor C_H1, with the stored charge represented as C_H1 × V_RBL. In the subsequent phase (Φ₂), switch S₂ is turned on, grounding the top source line (SL_T) and setting the bottom source line (SL_B) to V_READ. This causes holding capacitor C_H2 to retain the charge corresponding to the complementary data stored ${\mathrm{C}}_{\mathrm{H2}}\times \overline{{\mathrm{V}}_{\mathrm{RBL}}}$ . Since data is stored at the resistive divider node, when SL_T is activated, if the data is ‘0’, the activation of SL_B will read as ‘1’, and vice versa. Thus, these two phases allow the two capacitors to hold charges for both the stored data and its complementary value.

In the final phase (Φ₃), switch S₃ is closed, initiating charge sharing between the two capacitors, C_H1 and C_H2. Since both capacitors hold charges corresponding to the stored data and its complementary value at the RBL, the charge-sharing process results in both capacitors holding the average of these charges, assuming both capacitors are of equal value. This average represents the midpoint between the stored data values of ‘0’ and ‘1’ for the specific bitcell. The final voltage after charge sharing serves as the threshold for the sense amplifier, enabling the normal read operation. Depending on the stored data, the sense amplifier outputs ‘0’ if the data is ‘0’, or ‘1’ if the data is ‘1’.

Figure 10 depicts the self-referencing read operation for two bitcells: one storing ‘0’ connected to RBL1 and another storing ‘1’ connected to RBL2. During the first phase (Φ₁), S₁, SL_T, and RWL are activated. Since the bitcell linked to RBL1 stores ‘0’, its access transistor remains off, keeping RBL1 near GND, whereas RBL2 charges due to its active access transistor. In the second phase (Φ₂), the source line polarities are reversed-SL_T is grounded, and SL_B is activated along with RWL. Consequently, RBL1 charges while RBL2 stays near GND. The respective bitline voltages are stored on capacitors C_H1 and C_H2 during these phases. In the final phase (Φ₃), activating S₃ facilitates charge sharing between the capacitors, generating an average voltage that serves as the sense amplifier’s threshold. This ensures that any mismatch is compensated, placing the reference at the midpoint between the stored data and its complement. The sense amplifier then determines the final readout. The figure demonstrates that across 1000 Monte Carlo simulations, OUT1 correctly resolves to ‘0’ for the bitcell connected to RBL1, while OUT2 resolves to ‘1’ for the bitcell connected to RBL2.

Fig. 10 [Images not available. See PDF.]

Functional validation of the self-referencing read mechanism for two bitcells storing ‘0’ and ‘1’, utilizing a three-phase process of charge storage, source line polarity reversal, and charge sharing to produce a dynamic, bitcell-specific reference for the sense amplifier.

The distribution of the difference between the read bitline voltage and the dynamically generated threshold voltage by the self-referencing circuit is shown in Fig. 11. The results indicate that across 1000 Monte Carlo simulations, considering a 3-sigma process variation, the worst-case standard deviation of these differences is approximately 10.2 mV. This demonstrates the robustness of the proposed self-referencing technique, enabled by the voltage-divider FTJ-based bitcell structure.

Fig. 11 [Images not available. See PDF.]

Distribution of the read bitline voltage difference from the self-referenced threshold across 1000 Monte Carlo simulations, validating the robustness of the proposed technique.

Content-addressable memory (CAM) operation functionality

Figure 12a depicts the content-addressable memory (CAM) bitcell configuration enabled by our proposed FTJ-based bitcell array. Since the array shares source lines (SL_Ts and SL_Bs) across rows, these lines can also function as search lines for CAM operations. However, as data is typically input through row lines, enabling CAM functionality requires storing data in a transposed manner (column-wise instead of row-wise). This allows the shared source lines to serve as search line inputs while the read bitlines act as match lines. Figure 12b demonstrates parallel CAM operation at the array level, where data is provided via source lines, and activating specific row wordlines enables a search between the input and stored data.

Fig. 12 Content-addressable memory (CAM) configuration enabled by the proposed FTJ-based bitcell array. [Images not available. See PDF.]

a Single-bitcell CAM operation, where source lines serve as search lines and read bitlines act as match lines. b Parallel CAM operation at the array level, enabling search functionality by comparing stored and input data in a transposed manner.

The table in Fig. 12a demonstrates the CAM functionality of a single bitcell for different combinations of search input and stored data. To perform CAM operations, the input data (D) and its complement (DB) are applied to the bottom and top source lines, respectively. When both the input and stored data are ‘0’, DB is set to VDD, making R₂ equal to R_L. As a result, the read access transistor remains OFF, preventing any charge accumulation on the match line (ML), which stays close to GND, leading the sense amplifier to output ‘0’. Similarly, when both the input and stored data are ‘1’, D is set to VDD, making R₁ equal to R_L, again keeping the read access transistor OFF and ML at GND, producing a ‘0’ at the sense amplifier output. Thus, when the input data matches the stored data, the CAM circuit outputs ‘0’.

When the input search data and stored data do not match, the match line (ML) undergoes charging, causing the peripheral sense amplifier to output ‘1’, indicating a mismatch. For example, if the input data is ‘1’ while the stored data is ‘0’, D is set to VDD, making R₁ equal to R_H, which turns the access transistor ON. Similarly, if the input data is ‘0’ and the stored data is ‘1’, DB is set to VDD, making R₂ equal to R_H, also activating the access transistor. In summary, any mismatch results in charging of ML, enabling the peripheral sense amplifier to detect discrepancies between stored and search data. Thus, at the array level, as shown in Fig. 12b, binary CAM operation is performed between the search data sent via the source lines in parallel and the stored data arranged in a transposed manner, with each read bitline (match line) facilitating the comparison (‘0’ for match, and ‘1’ for any bit mismatch).

Figure 13 presents the Monte Carlo verification results for CAM operation across different combinations of stored and input search data. In Fig. 13a, when both the stored data and search input are ‘0’, the read bitline (RBL, acting as the match line ML) remains near GND, leading the sense amplifier to output ‘0’, indicating a match. Likewise, Fig. 13d illustrates a match scenario where both stored and search data are ‘1’. Conversely, Fig. 13b and c depict mismatch conditions, where the sense amplifier outputs ‘1’. In Fig. 13b, the read bitline surpasses the sense amplifier’s threshold when the stored data is ‘1’ and the search input is ‘0’, signaling a mismatch. Similarly, Fig. 13c illustrates a ‘1’ output from the sense amplifier when the stored data is ‘0’ and the search input is ‘1’. Across all 1000 Monte Carlo simulations for each bit combination, the results confirm that our proposed circuit effectively operates as a CAM, outputting ‘1’ for mismatches and ‘0’ for matches.

Fig. 13 Monte Carlo verification of CAM functionality for different input and stored data combinations. [Images not available. See PDF.]

a, d Match scenarios where the sense amplifier outputs ‘0’, while b, c mismatch cases where the read bitline exceeds the threshold, leading to a ‘1’ output.

Note, the same memory array can be dynamically reconfigured to operate in both standard memory and CAM modes without requiring physical reprogramming or restructuring. For instance, in standard memory mode, a single row wordline (RWL) is activated, and the read operation is performed by activating the top source line (SL_T), grounding the bottom source line (SL_B), and sensing the bitline (RBL), as illustrated in Fig. 2a. To reconfigure the array for CAM mode, all RWLs are simultaneously activated, and the input data is applied through both the top and bottom source lines (SL_T and SL_B). In this mode, the bitline (RBL) functions as the match line (ML) and performs pattern matching with the transposed stored data. This dynamic mode switching is achieved by appropriately controlling the row and source line drivers and interpreting the column outputs accordingly. As such, no structural changes are required-only the control signals differ-enabling seamless reconfiguration between memory and CAM functionalities within the same memory array.

Performance metrics estimation and comparison

Table 1 summarizes a comparison of various FTJ devices reported in the literature, utilizing different material systems and structural configurations. Compared to these, our 3R-MoS₂-based device achieves a lower switching voltage while maintaining a favorable on/off ratio, along with promising endurance and retention characteristics. While direct measurements of endurance and retention were not conducted in this study, previous reports on 3R-MoS₂ devices demonstrate strong performance, reinforcing the viability of our design.

Table 1. Comparison of reported FTJ devices based on material systems and performance metrics

Material System	Switching	Endurance	Retention	ON/OFF	Reference
	Voltage (V)	(Cycles)	Time	Ratio
Hf0.5Zr0.5O2/Al2O3	+2.7/−2.2	>5 × 104	Not specified	~200	APL52
BaTiO3/Nb:SrTiO3	±3	Not specified	>104 s	~103	Nat. Commun.34
(111)-PZT (PbZr0.52Ti0.48O3)	±3.6/±4.0	>109	>104 s	200–300	Nat. Commun.53
CuCrP2S6-based FTJ	±1	>2 × 104	>5000 s	~1000	Nat. Commun.54
α-In2Se3 asymmetric FTJ	±4	>106	>104 s	>104	ACS Nano55
WTe2/α-In2Se3/Au FTJ	<2	Not specified	Not specified	~4.7 × 105	Nano Lett.56
3R-MoS2 (This Work)	±1.5	>10647	10 years49	1000

Bold values indicate results obtained exclusively in this work; non-bold values are taken from the cited references.

The write energy per bit is determined by the switching voltage, the device resistance state, and the duration of the write pulse required for a successful operation. In our case, using a 1.5 V write voltage (V_WRITE), device low-resistance state of 22 MΩ (worst-case scenario) and an estimated pulse duration of 1 ns, the calculated write energy is 0.10 fJ/bit. To estimate the read energy accurately for both memory states (‘0’ and ‘1’), we conducted Monte Carlo simulations using a commercial PDK (GlobalFoundries’ 22 nm FD-SOI technology node). The simulations incorporated energy consumption of the driver and read circuitry, yielding an average read energy of approximately 30.2 fJ/bit.

Note, 3R-MoS₂ FTJs operate via interlayer domain wall motion, rather than conventional ionic displacement. Therefore, we can estimate the operation speed based on prior work. In recent experimental work by Bian et al.⁴⁷, polarization switching was achieved with a pulse width as short as 53 ns under an electric field of ±0.246 V/nm. Furthermore, their molecular dynamics simulations revealed that domain walls in bilayer 3R-MoS₂ can move at speeds up to 3000 m/s. We estimate that the domain size in our device should be less than 5 μm; the corresponding switching time is estimated to be on the order of ~1 ns, indicating that our FTJ devices are capable of ultra-fast operation, even beyond the experimental value reported in the literature⁴⁷. There is also another research revealing that the interlayer charge transfer time can be as low as 2 ps⁴⁸. Although it is not directly related to the polarization switching time, we can still see the potential of ultra-fast switching time in 3R-MoS₂ devices.

Prior works on 3R-MoS₂ FTJs with similar material systems have reported excellent performance, including >10⁶ switching cycles and data retention over 10 years, attributed to the interlayer sliding ferroelectric mechanism^47,49. These results support the robustness and long-term stability of the devices used in our design. In addition, the proposed 3R-MoS₂ FTJs are advantageous for scaling due to their van der Waals layered nature. The devices reported here are bilayer, i.e., 1.5 nm thick, and still retain promising performance.

It has also been demonstrated that MoS₂ can be integrated onto CMOS-compatible platforms at process temperatures below 400 °C, which is a key requirement for BEOL compatibility to avoid damage to underlying metal interconnects⁵⁰. Chemical vapor deposition (CVD) and metal–organic chemical vapor deposition (MOCVD) techniques have also been developed to realize large-area growth of MoS₂ at 300 °C. However, there are still some challenges, one of which is the control of defects and pinning centers in as-grown samples. Some studies have demonstrated that the ferroelectric switching of 3R-MoS₂ is highly related to defects and pinning centers⁵¹, which are uncontrollable in as-grown samples. Thus, large uniformity and device-to-device variability remain major challenges for industrial deployment. However, our self-referencing circuit techniques offer robust data sensing that mitigates the effects of such variations.

Discussions

In this work, we present a novel multi-functional polymorphic memory based on 2D MoS₂ FTJ-based bitcell that extends beyond traditional non-volatile data storage to enable various functional operations. Our proposed polymorphic memory supports Boolean NOR and NAND operations, efficient batch read operations for ‘0’ and ‘1’, and a self-referencing mechanism for variation-robust read operations. Additionally, the memory can be reconfigured as a content-addressable memory (CAM), enabling massively parallel search operations. Notably, all these functionalities are achieved solely through peripheral circuit modulation, making the design highly adaptable. With its versatile computing capabilities and efficient memory operations, the proposed FTJ-based memory is well-suited for memory-centric applications and next-generation computing systems, offering a promising pathway toward high-performance and energy-efficient architectures.

Methods

Fabrication and characterization of 2D FTJ devices

Bulk 3R-phase molybdenum disulfide (MoS₂) crystals were procured from HQ Graphene. To obtain bilayer 3R- MoS₂ samples, mechanical exfoliation was performed under ambient conditions, depositing the flakes onto silicon substrates. Graphene flakes were similarly exfoliated. A polydimethylsiloxane (PDMS) stamp coated with polycarbonate (PC) polymer was employed to sequentially pick up those exfoliated 2D flakes. This assembly was then transferred onto a silicon substrate pre-patterned with gold electrodes. The transfer process was facilitated by heating the substrate to 185 °C, allowing the PC to melt and release the 2D heterostructures onto the target substrates. Residual PC was subsequently removed by rinsing with chloroform.

Electrical measurements were conducted using a probe station connected with a Keithley 2400 SourceMeter. Current–voltage (I–V) characteristics were recorded by sweeping the voltage from −1.5 V to +1.5 V. The resistive switching behavior is also obtained by sweeping the voltage from −1.5 V to +1.5 V. All electrical transport measurements were performed in the ambient environment.

Acknowledgements

This work was supported in part by the U.S. National Science Foundation under Award Nos. CCF-2319617 and ECCS-2339093.

Author contributions

A.J. conceptualized the idea. M.K. and K.A. designed and verified the circuits. H.Y. fabricated the FTJ devices, conducted electrical measurements, and led the creation of Fig. 1. C.S. contributed to the preparation of Fig. 1. Y.M. prepared silicon substrates with gold pre-patterns for the FTJ devices. Y.W. and A.J. supervised the overall research and reviewed the paper.

Data availability

No datasets were generated or analysed during the current study.

Competing interests

The authors declare that they have no financial, personal, or professional conflicts of interest that could have influenced the work reported in this paper. All results and conclusions are based solely on the data and analyses presented.

Publisher’s note Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

References

1. Wulf, WA; McKee, SA. Hitting the memory wall: Implications of the obvious. ACM SIGARCH Comput. Architect. News; 1995; 23, pp. 20-24. [DOI: https://dx.doi.org/10.1145/216585.216588]

2. Cho, K et al. Sram write-and performance-assist cells for reducing interconnect resistance effects increased with technology scaling. IEEE J. Solid-State Circuits; 2022; 57, pp. 1039-1048. [DOI: https://dx.doi.org/10.1109/JSSC.2021.3138785]

3. Oldiges, P et al. Chip power-frequency scaling in 10/7nm node. IEEE Access; 2020; 8, pp. 154329-154337. [DOI: https://dx.doi.org/10.1109/ACCESS.2020.3017756]

4. Sebastian, A et al. Memory devices and applications for in-memory computing. Nat. Nanotechnol.; 2020; 15, pp. 529-544.1:CAS:528:DC%2BB3cXlvFyltrY%3D [DOI: https://dx.doi.org/10.1038/s41565-020-0655-z] [PubMed: https://www.ncbi.nlm.nih.gov/pubmed/32231270]

5. Verma, N et al. In-memory computing: advances and prospects. IEEE Solid-State Circuits Mag.; 2019; 11, pp. 43-55. [DOI: https://dx.doi.org/10.1109/MSSC.2019.2922889]

6. Agrawal, A; Jaiswal, A; Lee, C; Roy, K. X-sram: enabling in-memory boolean computations in CMOS static random access memories. IEEE Trans. Circuits Syst. I; 2018; 65, pp. 4219-4232.

7. Agrawal, A et al. Xcel-ram: accelerating binary neural networks in high-throughput SRAM compute arrays. IEEE Trans. Circuits Syst. I; 2019; 66, pp. 3064-3076.

8. Pedretti, G; Ielmini, D. In-memory computing with resistive memory circuits: status and outlook. Electronics; 2021; 10, 1063.1:CAS:528:DC%2BB3MXitFSlurfK [DOI: https://dx.doi.org/10.3390/electronics10091063]

9. Pan, J et al. Recent progress of non-volatile memory devices based on two-dimensional materials. Chips; 2024; 3, pp. 271-295. [DOI: https://dx.doi.org/10.3390/chips3040014]

10. Wang, S et al. Two-dimensional ferroelectric channel transistors integrating ultra-fast memory and neural computing. Nat. Commun.; 2021; 12, 1:CAS:528:DC%2BB3MXnsVKntQ%3D%3D [PubMed: https://www.ncbi.nlm.nih.gov/pubmed/33397907][PubMedCentral: https://www.ncbi.nlm.nih.gov/pmc/articles/PMC7782550][DOI: https://dx.doi.org/10.1038/s41467-020-20257-2] 53.

11. Lone, AH et al. Multilayer ferromagnetic spintronic devices for neuromorphic computing applications. Nanoscale; 2024; 16, pp. 12431-12444.1:CAS:528:DC%2BB2cXhtl2ltrnE [PubMed: https://www.ncbi.nlm.nih.gov/pubmed/38904318][DOI: https://dx.doi.org/10.1039/D4NR01003E]

12. Chen, B et al. Spintronic devices for high-density memory and neuromorphic computing—a review. Mater. Today; 2023; 70, pp. 193-217. [DOI: https://dx.doi.org/10.1016/j.mattod.2023.10.004]

13. Kaiser, MdAbdullah-Al et al. Voltage controlled magnetic tunnel junction based ADC less processing-in-pixel forextreme edge intelligence. npj Unconv. Comput.; 2025; 2, 14. [DOI: https://dx.doi.org/10.1038/s44335-025-00029-1]

14. Zhang, Y; Zheng, Q; Zhu, X; Yuan, Z; Xia, K. Spintronic devices for neuromorphic computing. Sci. China; 2020; 63, pp. 128-130.

15. Apalkov, D; Dieny, B; Slaughter, JM. Magnetoresistive random access memory. Proc. IEEE; 2016; 104, pp. 1796-1830.1:CAS:528:DC%2BC1cXltVShsLo%3D [DOI: https://dx.doi.org/10.1109/JPROC.2016.2590142]

16. Cai, H; Bian, Z; Fan, Z; Liu, B; Naviner, L. Commodity bit-cell sponsored mram interaction design for binary neural network. IEEE Trans. Electron Devices; 2021; 69, pp. 1721-1726. [DOI: https://dx.doi.org/10.1109/TED.2021.3134588]

17. Pham, T-N; Trinh, Q-K; Chang, I-J; Alioto, M. Stt-bnn: a novel STT-MRAM in-memory computing macro for binary neural networks. IEEE J. Emerg. Sel. Top. Circuits Syst.; 2022; 12, pp. 569-579. [DOI: https://dx.doi.org/10.1109/JETCAS.2022.3169759]

18. Slesazeck, S; Mikolajick, T. Nanoscale resistive switching memory devices: a review. Nanotechnology; 2019; 30, 352003.1:CAS:528:DC%2BC1MXhsl2mtLfO [PubMed: https://www.ncbi.nlm.nih.gov/pubmed/31071689][DOI: https://dx.doi.org/10.1088/1361-6528/ab2084]

19. Lanza, M et al. Recommended methods to study resistive switching devices. Adv. Electron. Mater.; 2019; 5, 1800143. [DOI: https://dx.doi.org/10.1002/aelm.201800143]

20. Ielmini, D; Wong, H-SP. In-memory computing with resistive switching devices. Nat. Electron.; 2018; 1, pp. 333-343. [DOI: https://dx.doi.org/10.1038/s41928-018-0092-2]

21. Zink, B. R., Madhavan, A., Borders, W. A. & McClelland, J. Exploration of the viability of tin/tiox reram in computational random-access memory (cram). In 2024 IEEE International Conference on Rebooting Computing (ICRC), 1–9 (2024).

22. Zanotti, T et al. Reliability of logic-in-memory circuits in resistive memory arrays. IEEE Trans. Electron Devices; 2020; 67, pp. 4611-4615. [DOI: https://dx.doi.org/10.1109/TED.2020.3025271]

23. Pries, J; Stenz, C; Wei, S; Wuttig, M; Lucas, P. Structural relaxation of amorphous phase change materials at room temperature. J. Appl. Phys.; 2024; 135, 135101.1:CAS:528:DC%2BB2cXotV2ns74%3D [DOI: https://dx.doi.org/10.1063/5.0198312]

24. Le Gallo, M et al. Mixed-precision in-memory computing. Nat. Electron.; 2018; 1, pp. 246-253. [DOI: https://dx.doi.org/10.1038/s41928-018-0054-8]

25. Aflalo, N., Yalon, E. & Kvatinsky, S. Bitwise logic using phase change memory devices based on the pinatubo architecture. In 2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID), 583–586 (IEEE, 2024).

26. Hoffer, B et al. Stateful logic using phase change memory. IEEE J. Explor. Solid-State Comput. Devices Circuits; 2022; 8, pp. 77-83. [DOI: https://dx.doi.org/10.1109/JXCDC.2022.3219731]

27. Yang, Y et al. Large switchable photoconduction within 2d potential well of a layered ferroelectric heterostructure. Adv. Mater.; 2020; 32, 2003033.1:CAS:528:DC%2BB3cXhsVyis7fL [DOI: https://dx.doi.org/10.1002/adma.202003033]

28. Saha, AK; Si, M; Ye, PD; Gupta, SK. α-In₂Se₃ based ferroelectric-semiconductor metal junction for non-volatile memories. Appl. Phys. Lett.; 2020; 117, 183504.1:CAS:528:DC%2BB3cXit1Ois7zE [DOI: https://dx.doi.org/10.1063/5.0021395]

29. Xue, F et al. Giant ferroelectric resistance switching controlled by a modulatory terminal for low-power neuromorphic in-memory computing. Adv. Mater.; 2021; 33, 2008709.1:CAS:528:DC%2BB3MXptVKks7k%3D [DOI: https://dx.doi.org/10.1002/adma.202008709]

30. Chen, L; Pam, ME; Li, S; Ang, K-W. Ferroelectric memory based on two-dimensional materials for neuromorphic computing. Neuromorphic Comput. Eng.; 2022; 2, 022001. [DOI: https://dx.doi.org/10.1088/2634-4386/ac57cb]

31. Zhang, H; Li, D; He, F; Chen, X. Development of an indirect thrust stand based on a cantilever beam. AIP Adv; 2021; 11, 035006. [DOI: https://dx.doi.org/10.1063/5.0041530]

32. Park, MH et al. Ferroelectricity and antiferroelectricity of doped thin HfO2-based films. Adv. Mater.; 2015; 27, pp. 1811-1831.1:CAS:528:DC%2BC2MXlsVKnsL0%3D [PubMed: https://www.ncbi.nlm.nih.gov/pubmed/25677113][DOI: https://dx.doi.org/10.1002/adma.201404531]

33. Berdan, R et al. Low-power linear computation using nonlinear ferroelectric tunnel junction memristors. Nat. Electron.; 2020; 3, pp. 259-266. [DOI: https://dx.doi.org/10.1038/s41928-020-0405-0]

34. Ma, C et al. Sub-nanosecond memristor based on ferroelectric tunnel junction. Nat. Commun.; 2020; 11, 1:CAS:528:DC%2BB3cXlt1Witr8%3D [PubMed: https://www.ncbi.nlm.nih.gov/pubmed/32188861][PubMedCentral: https://www.ncbi.nlm.nih.gov/pmc/articles/PMC7080735][DOI: https://dx.doi.org/10.1038/s41467-020-15249-1] 1439.

35. Jia, Y et al. Giant tunnelling electroresistance in atomic-scale ferroelectric tunnel junctions. Nat. Commun.; 2024; 15, 1:CAS:528:DC%2BB2cXivVWhurc%3D [PubMed: https://www.ncbi.nlm.nih.gov/pubmed/38267445][PubMedCentral: https://www.ncbi.nlm.nih.gov/pmc/articles/PMC10808203][DOI: https://dx.doi.org/10.1038/s41467-024-44927-7] 693.

36. Joo, Y; Hwang, E; Hong, H; Cho, S; Yang, H. Memory and synaptic devices based on emerging 2d ferroelectricity. Adv. Electron. Mater.; 2023; 9, 2300211.1:CAS:528:DC%2BB3sXht1KksrrN [DOI: https://dx.doi.org/10.1002/aelm.202300211]

37. Sun, H et al. Bifeo3-based flexible ferroelectric memristors for neuromorphic pattern recognition. ACS Appl. Electron. Mater.; 2020; 2, pp. 1081-1089.1:CAS:528:DC%2BB3cXlt1Sjtrs%3D [DOI: https://dx.doi.org/10.1021/acsaelm.0c00094]

38. Yang, Y et al. Atomic-scale fatigue mechanism of ferroelectric tunnel junctions. Sci. Adv.; 2021; 7, eabh2716.1:CAS:528:DC%2BB3MXislCntLrL [PubMed: https://www.ncbi.nlm.nih.gov/pubmed/34818041][PubMedCentral: https://www.ncbi.nlm.nih.gov/pmc/articles/PMC8612688][DOI: https://dx.doi.org/10.1126/sciadv.abh2716]

39. Guo, R et al. Functional ferroelectric tunnel junctions on silicon. Sci. Rep.; 2015; 5, 1:CAS:528:DC%2BC2MXhtlCjtrjL [PubMed: https://www.ncbi.nlm.nih.gov/pubmed/26215429][PubMedCentral: https://www.ncbi.nlm.nih.gov/pmc/articles/PMC4517170][DOI: https://dx.doi.org/10.1038/srep12576] 12576.

40. Garcia, V; Bibes, M. Ferroelectric tunnel junctions for information storage and processing. Nat. Commun.; 2014; 5, 1:CAS:528:DC%2BC2cXitVWgsb3I [PubMed: https://www.ncbi.nlm.nih.gov/pubmed/25056141][DOI: https://dx.doi.org/10.1038/ncomms5289] 4289.

41. Li, L; Wu, M. Binary compound bilayer and multilayer with vertical polarizations: two-dimensional ferroelectrics, multiferroics, and nanogenerators. ACS Nano; 2017; 11, pp. 6382-6388.1:CAS:528:DC%2BC2sXpslCltb8%3D [PubMed: https://www.ncbi.nlm.nih.gov/pubmed/28602074][DOI: https://dx.doi.org/10.1021/acsnano.7b02756]

42. Bennett, D. Theory of polar domains in Moiré heterostructures. Phys. Rev. B; 2022; 105, 235445.1:CAS:528:DC%2BB38XhvFSrs7fL [DOI: https://dx.doi.org/10.1103/PhysRevB.105.235445]

43. Gao, Y et al. Tunnel junctions based on interfacial two dimensional ferroelectrics. Nat. Commun.; 2024; 15, 1:CAS:528:DC%2BB2cXht1CksLbN [PubMed: https://www.ncbi.nlm.nih.gov/pubmed/38789446][PubMedCentral: https://www.ncbi.nlm.nih.gov/pmc/articles/PMC11126694][DOI: https://dx.doi.org/10.1038/s41467-024-48634-1] 4449.

44. Yang, D et al. Spontaneous-polarization-induced photovoltaic effect in rhombohedrally stacked MOS2. Nat. Photonics; 2022; 16, pp. 469-474.1:CAS:528:DC%2BB38XhsVSnsLnL [DOI: https://dx.doi.org/10.1038/s41566-022-01008-9]

45. Wu, M; Li, J. Sliding ferroelectricity in 2d van der Waals materials: related physics and future opportunities. Proc. Natl Acad. Sci. USA; 2021; 118, e2115703118. [PubMed: https://www.ncbi.nlm.nih.gov/pubmed/34862304][PubMedCentral: https://www.ncbi.nlm.nih.gov/pmc/articles/PMC8685923][DOI: https://dx.doi.org/10.1073/pnas.2115703118]

46. Stern, M et al. Interfacial ferroelectricity by van der Waals sliding. Science; 2021; 372, pp. 1462-1466. [DOI: https://dx.doi.org/10.1126/science.abe8177]

47. Bian, R et al. Developing fatigue-resistant ferroelectrics using interlayer sliding switching. Science; 2024; 385, pp. 57-62.1:CAS:528:DC%2BB2cXitVenu73E [PubMed: https://www.ncbi.nlm.nih.gov/pubmed/38843352][DOI: https://dx.doi.org/10.1126/science.ado1744]

48. Wu, J et al. Ultrafast response of spontaneous photovoltaic effect in 3R-MOS2–based heterostructures. Sci. Adv.; 2022; 8, eade3759.1:CAS:528:DC%2BB3sXhvFSltLs%3D [PubMed: https://www.ncbi.nlm.nih.gov/pubmed/36525495][PubMedCentral: https://www.ncbi.nlm.nih.gov/pmc/articles/PMC9757740][DOI: https://dx.doi.org/10.1126/sciadv.ade3759]

49. Li, X et al. Sliding ferroelectric memories and synapses based on rhombohedral-stacked bilayer MOS2. Nat. Commun.; 2024; 15, 1:CAS:528:DC%2BB2MXnvVOgtg%3D%3D [PubMed: https://www.ncbi.nlm.nih.gov/pubmed/39738177][PubMedCentral: https://www.ncbi.nlm.nih.gov/pmc/articles/PMC11685460][DOI: https://dx.doi.org/10.1038/s41467-024-55333-4] 10921.

50. Shen, Y et al. The trend of 2d transistors toward integrated circuits: scaling down and new mechanisms. Adv. Mater.; 2022; 34, 2201916.1:CAS:528:DC%2BB38Xis1yqtL7J [DOI: https://dx.doi.org/10.1002/adma.202201916]

51. Yang, D et al. Non-volatile electrical polarization switching via domain wall release in 3R-MOS2 bilayer. Nat. Commun.; 2024; 15, 1:CAS:528:DC%2BB2cXksVWru74%3D [PubMed: https://www.ncbi.nlm.nih.gov/pubmed/38360848][PubMedCentral: https://www.ncbi.nlm.nih.gov/pmc/articles/PMC10869714][DOI: https://dx.doi.org/10.1038/s41467-024-45709-x] 1389.

52. Cao, Y; Xiao, J; Qiao, H; Zhang, W; Li, Y. Ferroelectric tunnel junction based on Zr_0.75Hf_0.25O₂/Al₂O₃ composite barrier. Appl. Phys. Lett.; 2025; 126, 062904.1:CAS:528:DC%2BB2MXjvFOhtLo%3D [DOI: https://dx.doi.org/10.1063/5.0250527]

53. Luo, Z et al. High-precision and linear weight updates by subnanosecond pulses in ferroelectric tunnel junction for neuro-inspired computing. Nat. Commun.; 2022; 13, 1:CAS:528:DC%2BB38XivV2mu7g%3D [PubMed: https://www.ncbi.nlm.nih.gov/pubmed/35121735][PubMedCentral: https://www.ncbi.nlm.nih.gov/pmc/articles/PMC8816951][DOI: https://dx.doi.org/10.1038/s41467-022-28303-x] 699.

54. Ma, Y et al. High-performance van der Waals antiferroelectric CuCrP2S6-based memristors. Nat. Commun.; 2023; 14, 1:CAS:528:DC%2BB3sXisFSls7vM [PubMed: https://www.ncbi.nlm.nih.gov/pubmed/38036500][PubMedCentral: https://www.ncbi.nlm.nih.gov/pmc/articles/PMC10689492][DOI: https://dx.doi.org/10.1038/s41467-023-43628-x] 7891.

55. Si, M et al. Asymmetric metal/α-In2Se3/Si crossbar ferroelectric semiconductor junction. ACS Nano; 2021; 15, pp. 5689-5695.1:CAS:528:DC%2BB3MXlsVOmt7o%3D [PubMed: https://www.ncbi.nlm.nih.gov/pubmed/33651607][DOI: https://dx.doi.org/10.1021/acsnano.1c00968]

56. Li, Y et al. Nonvolatile memory device based on the ferroelectric metal/ferroelectric semiconductor junction. Nano Lett.; 2025; 25, pp. 1680-1688.1:CAS:528:DC%2BB2MXht1Cit7s%3D [PubMed: https://www.ncbi.nlm.nih.gov/pubmed/39811942][DOI: https://dx.doi.org/10.1021/acs.nanolett.4c05887]