1. Introduction How to obtain a high-power density power supply is becoming more and more attractive in the world. By increasing the switching frequency, the size of magnetic devices and capacitors can be reduced so that high-power density requirements can be achieved. However, for the hard switching to be considered, the higher the switching frequency, the greater the switching loss and the more difficult the heat process. In addition, the switching loss under hard switching is proportional to the switching frequency. Consequently, the problem in high switching frequency is becoming more and more serious, thereby causing resonant and soft-switching converters to develop to reduce the switching loss. The conventional resonant converter is based on the inductor connected in series with the main switch or the capacitor connected in parallel with the main switch so as to form a resonant loop. As the voltage on or current in the switch is dropped to zero, the switch is switched to achieve zero voltage switching (ZVS) turn-on of the switch or zero current switching (ZCS) turn-off of the switch. Basically, this method can reduce the crossover area of voltage and current of the switch, thereby decreasing the switching loss. However, large voltage and current spikes increase the voltage and current stresses of switches as well as increase the conduction losses. Furthermore, in order to render the output voltage controlled at a desired value, the switching frequency is varied because the resonant time is fixed, causing the design of the filter to be difficult.
As the conventional resonant converter has the demerits mentioned above, the soft-switching converter is presented. The ZVS/ZCS pulse-width-modulation (PWM) converter [1,2,3] has put an auxiliary switch to the resonant loop of the resonant converter to make the resonant time point adjustable, thereby leading to fixed frequency control and making the design of the filter easy. However, the conduction loss is large because the resonant voltage on and current in the circuit elements are large. The operating principle of the ZVT/ZCT converter is that prior to turn-on of the main switch, the auxiliary switch is conducted, and hence the transient resonance occurs. As the voltage on or current in the main switch resonates to zero, the main switch is turned on to achieve ZVT turn-on or ZCT turn-off. As the auxiliary switch in the off-state, no resonance happens, leading to effectively reducing the voltage or current stress as well as conduction loss. In the literature [4,5], although the main switches have ZVS turn-on, the auxiliary switches still operate under hard switching. In the literature [6,7,8], although the main and auxiliary switches have ZVS turn-on, many components lead to an increase in cost. The operating behavior of the ZVZCT converter [9,10,11] is that the auxiliary switch has two transient resonances over one cycle so that the main switch has ZVT turn-on and ZCT turn-off. Indeed, this converter can reduce switching and conduction losses, and no additional voltage and current stresses on components. However, such a converter has complexity in control and a relatively large part count, leading to an increase in cost. Furthermore, as the ZVS or ZVT turn-on is relatively suitable for the metal-oxide-semiconductor field-effect transistor (MOSFET) switch [10], there are many studies on the MOSFET switch with ZVS or ZVT turn-on.
In addition, based on the above-mentioned, the ZVS pulse width modulation (PWM) converter, the ZVT converter, and the ZVZCT converter have individual disadvantages. Accordingly, the active clamp technique is developed, which is composed of an auxiliary switch in series with a capacitor. The work of [12] applies the synchronous rectifier to the ZVS active clamp forward converter to reduce the conduction loss. Another paper [13] applies the soft-switched synchronous rectifier to the ZVS active clamp forward converter to reduce the conduction loss as well as the switching loss. A further paper [14] applies the two-switch active clamp to a forward converter for high input voltage applications. The work of [15] applies the phase-shift control to the dual active clamp forward converter to reduce the conduction loss. The work of [16] utilizes the combination of active clamp and passive clamp to improve the light-load efficiency. A further paper [17] applies the secondary-side resonance scheme to the active clamp flyback converter to shape the primary-side current waveform, and hence to reduce the primary-side root-mean-square (RMS) value. Another paper [18] employs the primary-side digital control to regulate the active lamp flyback converter. The work of [19] applies the bidirectional concept to the ZVT active clamp boost converter. The work of [20] applies a coupled inductor to the ZVS active clamp boost converter. In the work of [21], the improved ZVS topology is applied to the active clamp buck converter. Although the converters shown in [19,20,21] have ZVS or ZVT turn-on of the main switches, the number of components used is large, leading to an increase in cost as well as difficulty in circuit analysis. In addition, in CCM, there is no ZCS turn-off of the output diode, leading to a problem in reverse recovery current created from the output diode, which operates during the turn-off period.
Based on the aforementioned, in this paper, one traditional boost converter along with one auxiliary circuit is presented. This auxiliary circuit is composed of one auxiliary switch, one resonant inductor, and one active clamp capacitor, so that the main switch and the auxiliary switch are turned on with ZVS and the output diode is turned off with ZCS, thereby resulting in upgrading the overall efficiency. Furthermore, the proposed active clamp has a function of voltage clamp, thereby leading to reducing the voltage spike on the main switch to some extent, whereas this structure can also cause the output diode to have ZCS turn-off, thereby removing the reverse recovery current. Above all, the proposed auto-tuning technique of the second blanking time is applied to the proposed circuit to upgrade the overall efficiency further. By the way, the potential application of the proposed soft switching converter is for high-power light-emitting diode (LED) lighting fed by the direct current (DC) voltage to improve the overall efficiency [22].
2. Methodology 2.1. Proposed Converter
Figure 1 displays the proposed active clamp boost converter, which is constructed by one conventional boost converter combined with one auxiliary circuit. The former is built up by one input inductor Lin and one main switch S1, along with one body diode Ds1, one parasitic capacitor Cs1, one output diode Do, and one output capacitor Co. The latter is constructed by one auxiliary switch S2 along with one body diode Ds2, one parasitic capacitor Cs2, one resonant inductor Lr, and one active clamp capacitor Cc. The load is represented by one output resistor R. In addition, Figure 2 displays the equivalent circuit of the circuit shown in Figure 1, based on the assumption that the values of Co and Cc are large enough to be regarded as ideal voltage sources, whereas the value of Lin is large enough to be viewed as an ideal current source.
2.2. Operation Principles
2.2.1. Circuit Behavior
Prior to this section, the symbols and assumptions associated with the circuit displayed in Figure 1 and Figure 2 are given as follows: (i) Vin, Vo, and Vc are the dc input voltage, dc output voltage, and the dc voltage clamp voltage, respectively; (ii) Iin is the dc input current; (iii) iLr is the current in Lr and Do; (iv) vds1 and ids1 are the voltage on and current in S1, respectively; (v) vds1 and ids2 are the voltage on and current in S2, respectively; and (vi) all the elements are ideal except that switches have individual body diodes and parasitic capacitors. There are nine stages in the converter operating shown in Figure 3, where ton is the turn-on time of vgs1, which is equal to DTs with a switching period of Ts and a duty cycle of D, whereas toff is the turn-off time of vgs1, which is equal to (1−D)Ts.
Stage 1: (t0≤t≤t1)
As illustrated in Figure 3 and Figure 4, S1 is ON but S2 is OFF. During this stage, Lin is magnetized by Vin. At the same time, vds2 is clamped at Vc. Once S1 is cut off, the operation moves to stage 2.
Stage 2: (t1≤t≤t2)
As illustrated in Figure 3 and Figure 5, S1 is cut off and S2 is still OFF. During this state, Cs1 is abruptly charged to Vc. As Vc = vds1 + vds2, Cs2 is abruptly discharged to zero. At the same time, Lr is magnetized and the energy at input terminal is transferred to the output terminal via Do. Once the energy stored in Cs2 is entirely exhausted, the operation proceeds to stage 3.
According to Figure 5b, three stage equations can be obtained as
Iin=Cs1dvds1(t)dt+iLr(t)−Cs2dvds2(t)dtVc=vds1(t)+vds2(t)vds1(t)=LrdiLr(t)dt+Vo
By assuming that two switches are identical, Cs1 = Cs2 = Cs. Moreover, the initial values of this stage are iLr(t1) = 0, vds1(t1) = 0 and vds2(t1) = Vc. By taking the Laplace transform of Equation (1), the following equations can be attained to be
ILr(s)=(1s−ss2+12Lr Cs)Iin−(1Lrs2+12Lr Cs)VoVds1(s)=(1s−ss2+12Lr Cs)Vo+(12Css2+12Lr Cs)IinVds2(s)=Vcs−(1s−ss2+12Lr Cs)Vo−(12Css2+12Lr Cs)Iin
By taking the inverse Laplace transform of Equation (2), the following equations can be attained to be
iLr(t)=Iin[1−cos ω1(t−t1)]−VoZ1sin ω1(t−t1)vds1(t)=Vo[1−cos ω1(t−t1)]+Iin Z1sin ω1(t−t1)vds2(t)=Vc−Vo[1−cos ω1(t−t1)]−Iin Z1sin ω1(t−t1)
where
ω1=12Lr Cs and Z1=Lr2Cs
Ifω1(t−t1)≅0, thencos ω1(t−t1)andsin ω1(t−t1)can be close to the following equations:
cos ω1(t−t1)≅1sin ω1(t−t1)≅ω1(t−t1)
Substituting Equation (5) into Equation (3) yields
vds2(t)≅Vc−Iin Z1 ω1(t−t1)
According to Equation (6) and vds(t2) = 0, the corresponding time elapsed T2 is
T2=t2−t1=1ω1(VcIin Z1)
Stage 3: (t2≤t≤t3)
As illustrated in Figure 3 and Figure 6, S1 and S2 are both still OFF. In the previous stage, vds1(t2) = Vc and vds2(t2) = 0. During this stage, iLr is smaller than Iin. Hence, DS2 is conducted, making vds1 still clamped at Vc. At the same time, the voltage across Lr is Vc − Vo, causing iLr to increase linearly. As soon as S2 is conducted, the operation goes to stage 4.
According to Figure 6b, one stage equation can be obtained as
LrdiLr(t)dt=Vc−Vo
As the initial value of this stage is iLr(t2) = ILr2, solving Equation (8) yields
iLr(t)=(Vc−Vo)Lr(t−t2)+ILr2
Since iLr(t3) = ILr3, the corresponding time elapsed T3 is
T3=t3−t2=(ILr3−ILr2)Vc−VoLr
Stage 4: (t3≤t≤t4)
As illustrated in Figure 3 and Figure 7, S1 is still OFF, but S2 is conducted. In the previous stage, vds2(t3) = 0. Therefore, S2 is conducted at t3 with ZVS. As Iin is still smaller than iLr, the voltage across Lr is still Vc−Vo, causing Lr to still be linearly magnetized. Once iLr = Iin, the operation proceeds to stage 5.
One stage equation can be obtained as shown in Figure 7b.
LrdiLr(t)dt=Vc−Vo
As the initial value of this stage is iLr(t3) = ILr3, solving Equation (11) yields
iLr(t)=(Vc−Vo)Lr(t−t3)+ILr3
Because iLr(t4) = Iin, the corresponding time elapsed T4 is
T4=t4−t3=(Iin−ILr3)Vc−VoLr
Stage 5: (t4≤t≤t5)
As illustrated in Figure 3 and Figure 8, S1 is still OFF, but S2 is still ON. Hence, the voltage across S1 is clamped at Vc. During this stage, iLr is larger than Iin, changing ids2 to the positive direction. At the same time, the voltage across Lr is still Vc−Vo, causing Lr to still be linearly magnetized. As soon as S2 is cut off, the operation goes to stage 6.
One stage equation can be obtained as shown in Figure 8b.
LrdiLr(t)dt=Vc−Vo
As the initial value of this stage is iLr(t4) = Iin, solving Equation (14) yields
iLr(t)=(Vc−Vo)Lr(t−t4)+Iin
Because iLr(t5) = ILr5, the corresponding time elapsed T5 is
T5=t5−t4=(ILr5−Iin)Vc−VoLr
Stage 6: (t5≤t≤t6)
As illustrated in Figure 3 and Figure 9, S1 is still OFF and S2 is cut off. During this stage, iLr is still large than Iin, hence Cs2 is abruptly charged to Vc and Cs1 is abruptly discharged to zero. At the same time, Lr begins to be demagnetized. The moment Cs1 is discharged to zero, this stage comes to an end and the next stage begins.
Three stage equations can be obtained as shown in Figure 9b.
Iin=Cs1dvds1(t)dt+iLr(t)−Cs2dvds2(t)dtVc=vds1(t)+vds2(t)vds1(t)=LrdiLr(t)dt+Vo
By assuming two switches are identical, Cs1 = Cs2 = Cs. Further, the initial values of this stage are iLr(t5) = ILr5, vds1(t5) = Vc and vds2(t5) = 0. Based on Equation (4) and by taking the Laplace transform of Equation (17), the following equations can be attained:
ILr(s)=Iins−ss2+12Lr Cs(Iin−ILr5)+1Lrs2+12Lr Cs(Vc−Vo)Vds1(s)=Vos+ss2+12Lr Cs(Vc−Vo)+12Css2+12Lr Cs(Iin−ILr5)Vds2(s)=Vcs−Vos−ss2+12Lr Cs(Vc−Vo)−12Css2+12Lr Cs(Iin−ILr5)
By taking the inverse Laplace transform, the following equations can be attained:
iLr(t)=Iin−(Iin−ILr5) cos ω1(t−t5)+(Vc−Vo)Z1 sin ω1(t−t5)vds1(t)=Vo+(Vc−Vo) cos ω1(t−t5)+(Iin−ILr5)Z1 sin ω1(t−t5)vds2(t)=Vc−Vo−(Vc−Vo) cos ω1(t−t5)−(Iin−ILr5)Z1 sin ω1(t−t5)
According to Equations (5) and (19), the equation of vds2(t) can be simplified to
vds2(t)≅(ILr5−Iin)Z1 ω1(t−t5)
According to Equation (20) and vds2(t6) = Vc, the corresponding time elapsed T6 is
T6=t6−t5=1ω1[Vc(ILr5−Iin)Z1]
Stage 7: (t6≤t≤t7)
As illustrated in Figure 3 and Figure 10, S1 and S2 are still OFF, In the previous stage, vds1 is equal to zero, whereas vds2 is equal to Vc. During this stage, iLr is still larger than Iin, making Ds1 conducted, hence vds2 still clamped at Vc. At the same time, the voltage across Lr is−Vo, causing Lr to be linearly demagnetized. As soon as S1 is conducted, this stage comes to an end and the next stage begins.
According to Figure 10b, one stage equation can be obtained as
LrdiLr(t)dt=−Vo
As the initial value of this stage is iLr(t6) = ILr6, solving Equation (22) yields
iLr(t)=ILr6−VoLr(t−t6)
Because iLr(t7) = ILr7, the corresponding time elapsed T7 is
T7=t7−t6=(ILr6−ILr7)VoLr
Stage 8: (t7≤t≤t8)
As illustrated in Figure 3 and Figure 11, S1 is conducted and S2 is still OFF. In the previous stage, Ds1 is conducted so S1 is switched on with ZVS at t7. As iLr is still larger than Iin, the voltage across Lr is still−Vo, causing Lr to be still linearly demagnetized. As iLr = Iin, this stage ends and the next stage starts.
According to Figure 11b, one stage equation can be obtained as
LrdiLr(t)dt=−Vo
As the initial value of this stage is iLr(t7) = ILr7, solving Equation (25) yields
iLr(t)=iLr7−VoLr(t−t7)
Because iLr(t8) = Iin, the corresponding time elapsed T8 is
T8=t8−t7=(ILr7−Iin)VoLr
Stage 9: (t8≤t≤t0+Ts)
As illustrated in Figure 3 and Figure 12, S1 is still ON but S2 is still OFF. Hence, vds2 is clamped at Vc. During this stage, iLr is smaller than Iin, changing ids1 to the positive direction. At the same time, the voltage across Lr is− Vo, causing Lr to still be linearly demagnetized. From Figure 3, it can be seen that, as iLr = 0, the output diode Do is cut off before the turn-off time point of vgs1, meaning that Do has ZCS turn-off. Once iLr = 0, this stage ends with the next cycle repeated.
According to Figure 12b, one stage equation can be obtained as
LrdiLr(t)dt=−Vo
As the initial value of this stage is iLr(t8) = Iin, solving Equation (28) yields
iLr(t)=Iin−VoLr(t−t8)
Because iLr(t0 + Ts) = 0, the corresponding time elapsed T9 is
T9=t0−t8=IinVoLr
If T8 plus T9, which is about T9, is smaller than ton, i.e., DTs, the resonant inductor Lr works in DCM, meaning that there is no reverse recovery current during the turn-off period of Do. Because vgs1 and vgs2 have two blanking times between them per cycle, if T9 is larger than ton, then at the instant when S1 is cut off, but S2 is still OFF, iLr will flow through Ds1. Once S2 is turned on, a large reverse recovery current will flow through S2 owing to a reverse voltage of Vc across Ds1. Accordingly, S2 may be destroyed as a result of this current spike or S1 is turned on again, causing shoot-through between S1 and S2.
Table 1 is used to summarize soft switching types in the proposed converter.
2.2.2. Voltage Gain
By applying the voltage-second balance to Lin, we can obtain
1Ts∫tt+TsvLin(τ)dτ=Vin(D+α)+(Vin−Vc)(1−D−α)=0
By rearranging Equation (31), we can obtain
VcVin=11−D−α
where
α=T6+T7Ts
By applying the voltage-second balance to Lr, we can obtain
1Ts∫tt+TsvLr(τ)dτ=(Vc−Vo)(1−D−α)+(−Vo)(α+β)=0
By rearranging Equation (34), we can obtain
VoVc=1−D−α1−D+β
where
β=T8+T9Ts
Substituting Equation (35) into Equation (32) yields
VoVin=11−D+β
It can be seen from Equation (35) that the active clamp voltage Vc is larger than the output voltage Vo, whereas it can also be seen from Equation (37) that this voltage gain is smaller than that of the conventional boost converter in CCM. 2.3. Design Considerations
Table 2 shows the system specifications, whereas Table 3 shows the component specifications.
2.3.1. Design of Input Capacitance Co
As for output capacitor design, Equation (38) is used on condition that the maximum output voltage rippleΔvo,maxis equal to 0.1% of the output voltage Vo, the value of R is 17.6 Ω, Ts is 10 μs, D = 0.43, and Vo = 42 V. After some calculations, the value of Co is larger than 244 μF. Eventually, a 470 μF capacitor is chosen, because the value of the electrolytic capacitor will be decreased if the switching frequency is increased.
Co,min=VoDTsΔvo,maxR
2.3.2. Design of Input Inductance Lin
Because the converter operates in the CCM for any load, the minimum value of Lin, called Lin,min, can be represented by
Lin,min=RmaxD(1−D)2 Ts2
where Rmax = 176 Ω, D = 0.43, and Ts = 10 μs.
Based on Equation (39), Lin,min = 123 μH after some calculations and, eventually, the value of Lin is chosen to be 150 μH by considering the inductance reduction owing to the temperature and load. After this, a T175-18 core, manufactured by Micrometals, Inc. (Anaheim, CA, USA) is utilized, which has an inductance coefficient AL1 of 82 nH/N2, and hence the number of turns, called Nin, is
Nin=Lin×1000AL1=150×100082=42.76
Eventually, based on Equation (40), the value of Nin is chosen to be 43. 2.3.3. Design of Resonant Capacitance Cs
According to stage 2 in Section 2 with Cs1 = Cs2 = Cs, from Equation (7), we can obtain the following:
Vc=Iin×T22Cs
From Equation (32), we can get the relationship between Vin and Vc, with α being positive and smaller than 1, as shown in Equation (42):
Vc=Vin1−D−α>Vo
During stage 2, vds1 rises from zero to Vc and vds2 falls from Vc to zero. Based on the IRF540 datasheet and its characteristic curves of rising time tr and falling time tf versus drain current Ids, we can know that the value of T2 is about 0.02 μs. Hence, from Equations (41) and (42), we can attain the inequation of the resonance capacitance Cs to be
Cs<4.21×0.02 μs42×2=1 nF
As the resonant capacitance Cs is equal to the parasitic capacitance of the power switch, two IRF540 MOSFETs with typical output capacitance of 125 pF are chosen for S1 and S2 to meet the requirements of Equation (43). 2.3.4. Design of Resonant Inductance Lr
After the resonant capacitance Cs is determined, the design of the resonant inductance Lr will follow. As the resonant radian frequency ω1 is desired not to affect the operation behavior of the converter, the value of ω1 ten times larger than the value of the switching radian frequency ωs, namely,ω1>2π×106rad/sec. Therefore, based on Equations (43) and (44), the inequality of Lr can be obtained to be
Lr<12×(2π×106)2×Cs=12×(2π×106)2×10−9=12.6 μH
Accordingly, the value of Lr is chosen to be 10 µH. After this, a T175-18 core, manufactured by ARNOLD Co., is adopted, which has an inductance coefficient AL1 of 75 nH/N2, and hence the number of turns, called Nr, is
Nr=Lr×1000AL2=10×100075=11.55
Finally, based on Equation (45), the value of Nr is chosen to be 11. 2.3.5. Design of Active Clamp Capacitor Cc
Regarding the design of the active clamp capacitor Cc, it can be designed based on the required voltage ripple Δvc. From stages 2, 3, 4, 5, and 6 and Figure 3, it can be seen that Cc has the behavior of slight charge and discharge. Therefore, the product of Cc and Δvc can be expressed as
CcΔvc=ΔQc=12(ids2,max)(T5+T6)
where T5 and T6 are the times elapsed for stages 5 and 6, respectively.
Because individual switch parasitic capacitors in stages 2 and 6 have charge and discharge, the corresponding times elapsed are so short. Therefore, if two switches are identical, then
T6≅T2=0.02 μ
Accordingly, based on Equation (16), T5 plus T6 can be represented by
T5+T6=(ILr5−Iin)Vc−VoLr+0.02 μ
In order to find the value of Cc, the currents ids2,max and ILr5 should be figured out first. From stage 5 and Figure 8, the value of ids1,max can be obtained to be
ids2(t5)=ids2,max=iLr(t5)−Iin=ILr5−Iin
From Equation (49), the value of ILr5 should be figured out first, via stages 2 and 6 in Section 2.2.1. Based on Equations (7), (21) and (47), the following equation can be obtained to be
1ω1[Vc(ILr5−Iin)Z1]≅1ω1(VcIin Z1)
Rearranging Equation (50) yields
ILr5≅2Iin
Finally, substituting Equation (51) into Equation (49) yields
ids2,max≅2Iin−Iin=Iin
As Iin = Io,rated/(1-D), Iin can be obtained to be 4.165A from Table 2, if the voltage rippleΔvchas 5% of Vc, then, substituting Equations (48), (51), and (52) into Equation (46), the value of Cc can be expressed to be
Cc=86.94 μ+0.04 μVc0.05 Vc(Vc−42)
To solve the value of Cc, the value of Vc should be figured out first. From Figure 3, the following equation can be obtained:
∑n=27Tn=(1−D)Ts
Sequentially, from stage 2 in Section 2.2.1, the following equation can be obtained:
Iin=ids1(t2)+iLr(t2)−ids2(t2)
From Section 2.2.1, it can be seen that ids1(t2)=0 can be found and iLr(t2)≅0.22 A can be found based on Equation (3) and T2≅0.02 µs. Substituting ids1(t2)=0 and iLr(t2)≅0.22 A into Equation (55) yields
ids2(t2)≅−Iin
In addition, from stages 3 to 5, the voltage across Lr is Vc−Vo, thereby causing Lr to be linearly magnetized with iLr(t)=Iin+ids2(t), hence ids2(t) has the same slope from stages 3 to 5. Accordingly, based on the ampere-second balance, the following equation can be obtained:
T2+T3+T4≅T5+T6
From Equations (33) and (47), the following equation can be obtained:
T7=αTs−0.02 μ
Based on Equations (48), (54), (57), and (58), the following equation can be obtained:
∑n=27Tn=2×(ILr5−IinVc−VoLr+0.02 μ)+10 μα−0.02 μ=(1−D)Ts
Based on Table 2 and the obtained values, Equation (59) can be rewritten to be
210 μα2−161.08 μα+23.72 μ=0
Solving Equation (60) yields
α≅0.19,0.568
Ifα=0.568, this means that the auxiliary switch has only turn-on time of 0.02 μs. By considering the rising and falling times,αis chosen to be 0.19. Substitutingαinto Equation (32) yields
Vc=241−0.43−0.19=63.2 V
Substituting Equation (62) into Equation (53) yields
Cc=86.94 μ+0.04 μ×63.20.05×63.2(63.2−42)
Solving Equation (63) yields Cs≅1.33 µF. Eventually, the value of Cs is selected as 2.2 µF.
2.4. Digital Control Flow Chart
As shown in Figure 13a, there are five modules in the digital control strategy, including output voltage sampling, named V_sample; input current sampling, named I_sample; look-up table; digital controller; and digital pulse width modulation generator, named DPWM.
2.4.1. System Operation
In Figure 13a, the output voltage and the input current are sensed by the V_sample module and the I_sample module, respectively. The sensed output voltage is sent to the digital controller and then to the DPWM generator to create a suitable gate driving signal for the switch S1, so as to keep the output voltage constant at a desired value. The sensed current is sent to the look-up table to generate a suitable gate driving signal for the switch S2, so that the cut-off time point of the auxiliary switch S2 can be determined.
2.4.2. Auto Tuning of the Last Blanking Time of S2
From Section 2, we can see that as the auxiliary switch S2 is cut off, the resonant inductor Lr begins to be demagnetized, and the demagnetization path will pass through Do, leading to the power dissipation in Do. Accordingly, cutting off S2 early reduces the required time flowing through Do, hence the power dissipation in Do will be decreased, increasing the overall efficiency. Therefore, a lookup table is built up with the relationship between the cut-off time point of S2 and load current Io. However, it is noted that, as for the auto tuning of the cut-off time point for S2, the resonant current iLr should be larger than the input current Iin before the main switch S1 is switched on so as to make sure that S1 is switched on with ZVS. In the following, how to construct this lookup table is mentioned below.
Step 1
Under an open-loop test with ten points from light to rated load, the maximum efficiency for each sensed input current is obtained by manually tuning the cut-off time point of the auxiliary switch S2. This sensed input current is digitalized and then used to generate one interval value in a look-up table.
Step 2
For each point, the corresponding cut-off time point of S2 under the maximum efficiency is recorded.
Step 3
A lookup table with cut-off time point of S2 versus interval value created from the input current is established as shown in Figure 13b. After this, as an actual input current is sensed and digitalized; this value will be stored in the register REG and then compared with interval values in the lookup-up table to obtain the required cut-off time point of S2, called L_T. The corresponding gate driving signal for S2 is obtained as illustrated in Figure 14. Accordingly, the proposed converter will do a good performance on efficiency under different input current levels. It is noted that the hysteresis band is applied to the exchange of two cut-off time points to avoid oscillation.
It is noted that the proposed auto-tuning technique is used in the steady state. First, the input current Iin is sampled at a time point within the turn-on time ton of vgs1. After this, based on the lookup table, the corresponding cut-off time point of vgs2 for the auxiliary switch S2 will be determined, which will be used in the next cycle of vgs2. As to vgs1 for the main switch S1, it is almost not changed because the duty cycle of vgs1 is generated from the controller, hence the system stability is almost not affected. 3. Results and Discussion
At a rated load, Figure 15 shows the gate driving signals for S1 and S2, called vgs1 and vgs2, respectively. Figure 16 shows the gate driving signal for S1, called vgs1; the voltage on S1, called vds1; and the current in S1, called ids1. Figure 17 shows the gate driving signal for S2, called vgs2; the voltage on S2, called vds2; and the current in S2, called ids2. Figure 18 shows the voltage on Cc, called vc, and the current in Lr, called iLr. Figure 19 shows the voltage on Do, called vDo, and the current in Lr, called iLr. Figure 20 shows the efficiency comparison.
From Figure 15, it can be seen that vgs1 and vgs2 are complementary to each other. From Figure 16, before S1 is turned on, ids1 flows in the opposite direction, causing Cs1 to be discharged to zero, making Ds1 forward biased. At this moment, S1 is switched on with ZVS. From Figure 17, before S2 is turned on, ids2 flows in the opposite direction, causing Cs2 to be discharged to zero, making Ds2 forward biased. At this moment, S2 is switched on with ZVS. From Figure 18, it can be seen that vc is almost kept constant at about 60 V, close to Equation (62). In addition, according to Equation (30), the ideal value of T9 can be figured out to be
T9=IinVoLr=Io,rated LrVo(1−D)=2.38×1 μ42(1−0.43)=1 μs
From Equation (64), the ideal value of T9 is smaller than the ideal value of ton of vgs1, i.e., 4.3 μs. Moreover, from Figure 18, the calculated value of T9 is 1.36 μs, which is located between 1 μs and 4.3 μs. Therefore, we can confirm that the output diode has ZCS turn-off.
In the following, an efficiency test bench will be described as shown in Figure 19. First of all, the input current Iin is attained by measuring the voltage on one current-sensing resistor according to one digital meter. Afterwards, the input voltage Vin is also attained by another digital meter. Therefore, the input power can be attained. As to the output power, the output current Io is read from one electronic load and the output voltage Vo is also attained by the other digital meter. Thus, the output power can be attained. Eventually, the required efficiency can be attained. In Figure 20, there are three cases used for efficiency comparison. Case 1 is under soft switching with auto tuning of the turn-off time point of the auxiliary switch. Case 2 is only under soft switching without auto tuning of the turn-off time point of the auxiliary switch. Case 3 is only under the hard switching without auto tuning of the turn-off time point of the auxiliary switch. Therefore, at 10% load, all three have the same the second blanking time, leading to the efficiencies for cases 1 and 2 being the same. As the load is increased, only the second blanking time in case 1 is changed. From Figure 20, it can be seen that the proposed soft switching with auto tuning of the cut-off time point of the auxiliary switch has the best performance in efficiency among them.
4. Conclusions and Future Work The traditional boost converter, having an active clamp circuit along with the resonant inductor, is presented herein. Both the main switch and the auxiliary switch can be turned on with ZVS and the output diode can be turned off with ZCS. In addition, as the active clamp circuit is utilized, the voltage spike on the main switch can be suppressed to some extent, whereas because this structure, although the input inductor is designed in CCM, the output diode can operate with ZCS turn-off, leading to the resonant inductor operating in DCM, hence there is no reverse recovery current during the turn-off period of the output diode. Unlike the existing soft switching circuits, in order to improve the overall efficiency further, one look-up table is employed to adjust the cut-off time point of the auxiliary switch so that the current flowing through the output diode is reduced. By doing so, the maximum efficiency is 96.9%. In this paper, the cut-off time point of the auxiliary switch is adjusted only in the steady state. In the future, adjusting the cut-off time point for the auxiliary switch in the transient will be studied. In addition, the MOSFETs and Schottky diode used are all Si-based. For high switching frequency applications, SiC- or GaN-based semiconductors can be more attractive than Si-based ones. This will also be studied.
Enlarge this image.Figure 1. Proposed active clamp boost converter.
Enlarge this image.Figure 2. Equivalent circuit of the circuit shown in Figure 1.
Enlarge this image.Figure 3. Key waveforms pertaining to the working converter.
Enlarge this image.Figure 4.(a) Current path for stage 1; (b) equivalent of (a).
Enlarge this image.Figure 5.(a) Current path for stage 2; (b) equivalent of (a).
Enlarge this image.Figure 6.(a) Current path for stage 3; (b) equivalent of (a).
Enlarge this image.Figure 7.(a) Current path for stage 4; (b) equivalent of (a).
Enlarge this image.Figure 8.(a) Current path for stage 5; (b) equivalent of (a).
Enlarge this image.Figure 9.(a) Current path for stage 6; (b) equivalent of (a).
Enlarge this image.Figure 10.(a) Current path for stage 7; (b) equivalent of (a).
Enlarge this image.Figure 11.(a) Current path for stage 8; (b) equivalent of (a).
Enlarge this image.Figure 12.(a) Current path for stage 9; (b) equivalent of (a).
Enlarge this image.Figure 13.(a) System operation flow chart; (b) look-up table operation flow chart. PWM, pulse width modulation.
Enlarge this image.Figure 14. Auto-tuning technique with X and Y called the first blanking time and the second blanking time, respectively: (a) withX=Y; (b) withX≠Y.
Enlarge this image.Figure 15. Experimental waveforms: (1) vgs1; (2) vgs2.
Enlarge this image.Figure 16. Experimental waveforms: (1) vgs1; (2) vds1; (3) ids1.
Enlarge this image.Figure 17. Experimental waveforms: (1) vgs2; (2) vds2; (3) ids2.
Enlarge this image.Figure 18. Experimental waveforms: (1) vc; (2) iLr.
Enlarge this image.Figure 19. Efficiency test bench. (DC: direct current; FPGA: field programmable gate array).
Enlarge this image.Figure 20. Efficiency comparison.
| Interval | Stage | Type |
|---|---|---|
| t3≤t≤t4 | 4 | S2 ZVS turn-on |
| t7≤t≤t8 | 8 | S1 ZVS turn-on |
| t8≤t≤t0+Ts | 9 | Do ZCS turn-off |
| Scheme 24. | Specifications |
|---|---|
| Operation Mode | CCM |
| Input Voltage (Vin) | 24 V |
| Output Voltage (Vo) | 42 V |
| Ideal Duty Cycle (D) | 0.43 |
| Switching Frequency (fs) | 100 kHz |
| Output Rated Power (Po,rated)/Current (Io,rated) | 100 W/2.38 A |
| Output Minimum Power (Po,min)/Current (Io,min) | 10 W/0.238 A |
| Components | Specifications |
|---|---|
| Input Inductance (Lin) | 150 μH |
| Resonant Inductance (Lr) | 10 μH |
| Output Capacitance (Co) | 470 μF |
| Clamp Capacitance (Cc) | 2.2 μF |
| Power Switches (S1 and S2) | IRF540 |
| Output Diode (Do) | STPS20120C |
| Field Programmable Gate Array (FPGA) | EP2C20F484C8 |
Author Contributions
Conceptualization, Y.-T.Y.; methodology, K.-I.H.; software, Y.-K.T.; validation, Y.-T.Y.; formal analysis, Y.-T.Y.; investigation, Y.-K.T.; resources, Y.-T.Y.; data curation, Y.-K.T.; writing-original draft preparation, K.-I.H.; writing-review and editing, K.-I.H.; visualization, Y.-K.T.; supervision, K.-I.H.; project administration, K.-I.H.; funding acquisition, Y.-T.Y. All authors have read and agreed to the published version of the manuscript.
Funding
This research was funded by the Ministry of Science and Technology, Taiwan, under the Grant Number: MOST 109-2222-E-167-003-MY3.
Institutional Review Board Statement
Not applicable.
Informed Consent Statement
Not applicable.
Data Availability Statement
No new data were created or analyzed in this study. Data sharing is not applicable to this article.
Conflicts of Interest
The authors declare no conflict of interest.
Nomenclature
| S1 | Main switch |
| S2 | Auxiliary switch |
| Lin | Input inductor |
| Lr | Resonant inductor |
| Co | Output capacitor |
| Cc | Active clamp capacitor |
| Cs1 | Parasitic capacitor of S1 |
| Cs2 | Parasitic capacitor of S2 |
| Do | Output diode |
| Ds1 | Body diode of S1 |
| Ds2 | Body diode of S2 |
| R | Output resistor |
| Rmax | Maximum output resistance |
| ω1 | Resonant radian frequency |
| ωs | Switching radian frequency |
| Z1 | Characteristic impedance |
| Ts | Switching period |
| fs | Switching frequency |
| D | Duty cycle |
| Vin | Input dc voltage |
| Vo | Output dc voltage |
| Vc | Active clamp dc voltage |
| Δvo,max | Maximum output voltage ripple |
| Δvc | Active clamp voltage ripple |
| vc | Active clamp voltage |
| vgs1 | Gate driving signal for S1 |
| vgs2 | Gate driving signal for S2 |
| vds1 | Voltage across S1 |
| vds2 | Voltage across S2 |
| vDo | Voltage across Do |
| Iin | Input dc current |
| Iin,rated | Rated input dc current |
| Io | Output dc current |
| Io,rated | Rated output dc current |
| Io,min | Minimum output dc current |
| ids1 | Current flowing through S1 |
| ids2 | Current flowing through S2 |
| iLr | Current flowing through Lr |
| Po,rated | Rated output power |
| Po,min | Minimum output power |
| L_T | Auto-tuning of the cut-off time point of S2 |
| X | Front edge blanking time |
| Y | Back edge blanking time |
| α | T6 plus T7 divided by Ts |
| β | T8 plus T9 divided by Ts |
| t0tot0+Ts | Time points used in Figure 3 |
| T2toT9 | Elapsed times for operating stages |
| ILr2toIL r7 | Currents in Lr for time points in Figure 3 |
| ids2,max | Maximum current flowing through S2 |
| Nin | Number of turns for Lin |
| Nr | Number of turns for Lr |
| AL1 | Inductor coefficient for Lin |
| AL2 | Inductor coefficient for Lr |
| Lin,min | Minimum input inductance |
| ΔQc | Net charge in Cc |
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Yeu-Torng Yau
1,
Kuo-Ing Hwu
2,* and
Yu-Kun Tai
2
1Department of Ph.D. Program, Prospective Technology of Electrical Engineering and Computer Science, Department of Electrical Engineering, National Chin-Yi University of Technology, Taichung 41170, Taiwan
2Department of Electrical Engineering, National Taipei University of Technology, Taipei 10608, Taiwan
*Author to whom correspondence should be addressed.
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