An Adaptive Feed-Forward Phase Locked Loop for Grid Synchronization of Renewable Energy Systems under Wide Frequency Deviations

Abstract

Synchronization is a crucial problem in the grid-connected inverter’s control and operation. A phase-locked loop (PLL) is a typical grid synchronization strategy, which ought to have a high resistance to power system uncertainties since its sensitivity influences the generated reference signal. The traditional PLL catches the phase and frequency of the input signal via the feedback loop filter (LF). In general, to enhance the steady-state capability during distorted grid conditions generally, a filter tuned for nominal frequency is used. This PLL corrects large frequency deviations around the nominal frequency, which increases the PLL’s locking time. Therefore, this paper presents an adaptive feed-forward PLL, where the input signal frequency and phase under large frequency deviations are tracked precisely, which overcomes the above-mentioned limitations. The proposed adaptive PLL consists of a feedback loop that reduces the phase error. The feed-forward loop predicts the frequency and phase error, and the frequency adaptive FIR filter reduces the ripples in output, which is due to input distortions. The adaptive mechanism adjusts the gain of the filter in accordance with the supply frequency. This reduces the phase and frequency error and also decreases the locking time under wide frequency deviations. To verify the effectiveness of the proposed adaptive feed-forward PLL, the system was tested under different grid abnormal conditions. Further, the stability analysis has been carried out via a developed prototype test platform in the laboratory. To bring the proposed simulations into real-time implementations and for control strategies, an Altera Cyclone II field-programmable gate array (FPGA) board has been used. The obtained results of the proposed PLL via simulations and hardware are compared with conventional techniques, and it indicates the superiority of the proposed method. The proposed PLL effectively able to tackle the different grid uncertainties, which can be observed from the results presented in the result section.

1. Introduction

Renewable energy systems, such as solar photovoltaic and wind energy conversion systems, use power electronic converters to inject the generated power to the grid. While integrating these systems with the grid, synchronization is the critical phenomenon that plays a significant role [1,2]. For the effective operation of grid-connected converter, the maintaining phase and frequency of utility voltage are essential. A good synchronization scheme must proficiently detect the phase angle of the utility signal, track the phase and frequency variations smoothly, and forcefully reject disturbances and harmonics. Improper PLL design leads the system to unstable, and the output theta will get distorted, which leads to poor synchronization with an increase in the locking time. Despite various synchronization techniques that have been enforced in the literature [3,4], the well-known and widely used control technique for three-phase power systems is synchronous reference frame PLL (SRF-PLL) [5]. The SRF-PLL works basically with a mechanism of nonlinear feedback control, which effectively maintains the phase and magnitude of the input signal. It mainly comprises the phase detector (PD), voltage-controlled oscillator (VCO), and loop filter (LF). Phase information is obtained through the abc-to-dq transformation, and the system dynamics are determined by a loop filter. When the three-phase system is balanced, a high bandwidth PLL with a very fast transient response can be achieved [6]. In PLL, a PI controller is utilized as a loop filter [7]. A double frequency component in the stationary frame is introduced by a phase unbalancing in utility and generates a distorted reference signal. A reduction in the bandwidth of the PLL improves the system performance at the cost of increased response time [8]. The phase angle estimation is additionally implemented under large frequency deviations with a steady-state error. Obtaining zero steady-state error under dynamic conditions is a challenging task while developing PLLs for grid applications. To eradicate this problem, the authors in [9,10,11] have proposed the distinct combinations of filtering techniques into the PLL structure.

To eliminate the definite frequencies in the input signal, notch filters were designed in [12]. The double frequency ripples caused by unbalanced utility voltages are removed by employing a notch filter by the SRF PLL. Since the notch filter center frequency is fixed, any change in supply frequency from the nominal value will result in deterioration of system performance. One or more lead compensators [13] are cascaded with the PI controller to optimize the performance and improve the steady-state disturbance rejection capability of PLL. Phase tracking with lead compensators is faster than frequency tracking. Moving average filters [14] are employed to remove the ripple due to unbalance and harmonic conditions. In spite of advantages like the easy realization and low computational burden, its frequency-dependent attenuation characteristics degrade its performance.

In order to address the disadvantages of SRF PLL, an enhanced phase-locked loop structure with multiple filters [15] in series is proposed. The distortion components present in the input signal is attenuated through a chain of pre-filters, and a lead compensator is used to remove the phase lag introduced by various filters. Even though the decoupled double synchronous reference frame (DDSRF) PLL [16] eliminates the double frequency ripple, the implementation is complex and limited to canceling the effect of only a few harmonics. The PLL developed for FACTS applications consist of voltage magnitude blocks, phase angle block, and frequency block, which sets the system gain adaptively [17]. The independent frequency and phase tracking control structure provide a good response under large frequency variations. An additional sub-filter is added in the adaptive linear optimal filter (ALOF) [18] to remove the harmonic components and individual harmonics. The frequency is recursively modified by the algorithm and the input signal phase angle, and the learning rate parameter reconciles the accuracy with the convergence speed. Major modification introduced by the enhanced PLL [19] in the phase detector section is used in power system applications for frequency measurements. In most of these methods [12,13,14,15,16,17,18], the nominal frequency correction is provided by the loop filter. Until an adjustment is made for the filtering characteristics under large frequency deviations, the dynamic response is the system will reduce.

In addition to the feedback loop, a feed-forward loop is introduced as an attempt in [20,21] to increase the dynamic performance of PLL. The reference signal is tracked with a lesser tracking error due to the addition of a second control path and lowers the response time [22]. Due to the presence of feedback loop and feed-forward loop action in the classical quadrature PLL (qPLL) [21], the phase-locking time is reduced in the start-up stage. The performance of the PLL in unbalanced conditions is better than the performance of conventional PLL systems. The introduction of a feed-forward path minimizes the frequency error and improves the dynamic performance in the feed-forward frequency PLL (FPLL) [20,23]. The performance under large frequency deviations still deteriorates since the consideration of a moving average filter, which improves filtering characteristics. Thus to overcome this issue, a filter is required to change its filter coefficient and ripple even under a large change in frequency.

This paper is a supplement to [20] and uses an adaptive frequency FIR filter to enhance the tracking capability of the PLL under wide variation in frequency and reduce the double frequency oscillations. In the proposed control, for wide frequency deviations, the phase and input frequency are effectively tacked by the developed synchronization technique. By using the adaptive filter, the dynamic feed-forward estimator loop enables frequency error elimination and ripple removal even under wide frequency deviations. The highlights of the proposed frequency adaptive PLL are, the feedback loop of the proposed PLL eliminates the phase error, the feed-forward loop of the proposed PLL predicts the frequency error, and the adaptive frequency filter reduces the ripples and dual-frequency oscillations. To assess the effectiveness of the proposed PLL over conventional technique, the examinations are conducted under different grid conditions such as ramp change in frequency, phase jump, harmonics, and phase unbalance.

The paper is arranged as follows: The second section describes the structure of the proposed Phase Locked Loop. Section 3 analyzes the small-signal modeling of the proposed feed-forward Phase Locked Loop, performance analysis of the proposed PLL is described in Section 4. Section 5 is a detailed explanation for all the simulated and experimental studies under grid abnormal conditions such as harmonics phase Jump, frequency deviation, and unbalance condition. Finally, Section 6 highlights the most important conclusions.

2. System Description

The basic block diagram of the grid-connected photovoltaic system is shown in Figure 1a. The solar photovoltaic system is connected to the gird through a DC/DC converter and an IGBT-based inverter. To synchronize the inverter with a grid, the phase-locked loop plays a major role in the inverter control. Generally, a basic synchronous reference frame based phase-locked loop is used. The basic SRF phase-locked loop tracks the input signal phase and frequency using the closed-loop feedback control loop.

The phase detector generates an error signal with reference to the difference between input and feedback signal, and the loop filter is generally a PI controller that filters the error signal. The center frequency of VCO is fixed at a nominal frequency (feed-forward constant), and the function of the VCO is to generate a signal of frequency (Δω) at the point when the input frequency veers off from the nominal frequency. When a supply frequency has a significant deviation from the nominal value, the locking time increases considerably. Since ∆ω << ω_ff, if ω_ff is updated as a function of the supply frequency, the frequency error is easily eliminated, and the loop filter can reduce only the phase error, which reduces the response time of PLL.

As shown in Figure 1b, in addition to the feedback loop, the feed-forward frequency PLL (FPLL) consists of a feed-forward loop. The center frequency of the VCO is dynamically adjusted by the feed-forward loop, and thus the center frequency of the VCO varies under frequency deviations, and the correction to be made by the feedback loop decreases. Therefore, this control technique increases the dynamic efficiency of the PLL under a significant variation in input frequency from the nominal value.

A filter is used to create an undistorted output along with the PI controller even under uncertain utility scenarios, namely phase shift, unbalance, and harmonics. In FPLL, a moveable average filter is used to removes the numerous frequencies ripple due to distorted utility conditions. The moving average filter (MAF) having the capability of eliminating any ripple, which is multiple of its intended frequency. Therefore, the harmonics and double frequency ripples are easily canceled out by using MAF. The frequency-dependent attenuation characteristics are exhibited, which is considered as the major problem with MAF. The ripples due to disturbances change while the changes in supply frequency. In such cases, the disturbance components are not completely blocked by the MAF, and PLL reveals spoor results.

To improve the filtering characteristics, an adaptive frequency moving average filter is essential. Figure 2 illustrates the structure of adaptive FPLL for grid synchronization.

To design a frequency-adaptive moving average filter, several methods [24,25] have been proposed. The adaptive MAF can be obtained either by modifying the filter order with respect to the grid frequency fluctuation, or by adjusting the sampling frequency for the phase-locked loop with respect to the supply frequency, or by using the FIR coefficient in the form of a lookup table. In the proposed work, the coefficient of the Adaptive FIR (AFIR) filter is modified by using a lookup table. The lookup table provides frequency coefficients varying from 20 to 60 Hz for input supply. The frequency spectrum is broken down into 14 bands with each 3 Hz band. On that basis, the adaptive MAF filter automatically updates the filter coefficient, which enables the ripples to be diminished under distorted conditions.

3. Small Signal Modeling

The design of FPLL’s small-signal modeling is presented in this section. V_a, V_b, and V_c are the magnitude of the three-phase voltage.

[_VaVbVc]=[_Vmcosθ_Vmcos(θ−2π/3)_Vmcos(θ+2π/3)]

The transformation of these signals into the stationary reference frame signals V_α and V_β are done by Clarke transformation, and Park transformation is used for transforming to dq frame.

[_VαVβ]=2/3[1−1/2−1/20−3/23/2][_VaVbVc]

[_VdVq]=[cos^θ*−sin^θ*sin^θ*cos^θ*][_VαVβ]=V[cos(Δθ)sin(Δθ)]

where,

Δθ=^θ*−θ

and V is the magnitude.

Figure 3 shows the small-signal model of FPLL, where LPF(s) represents the first order low pass filter, LF(s) represent the transfer function of the loop filter, ∆ω represents the change in frequency from the nominal value of frequency in rad/s, D(s) represents the disturbance in the input signal, ω_ff and ω* are the feed-forward frequency, AFIR represents the Adaptive Finite Impulse Response filter and the estimated frequency. The θ_e(s), θ(s), and θ^(s) are the phase angle error, input angle, and estimated angle, respectively.

The low pass filter LPF₁ is given by

_LPF1(s)=_ωp/(s+_ωp)

A PI controller is connected to the low pass filter whose transfer function is given by

_Gc(s)=(_Kp+_KI/s)

From (5) and (6), the loop filter of FPLL is derived as

LF(s)=_{KP ωp}s+_{KI ωp}s(s+_ωp)

The FPLL’s open-loop transfer function is defined as

_Gol(s)=(_ωp ^s2+_{Kp Vωp}s+_{Ki Vωp}^s3)

The FPLL feed-forward frequency is

_ωff(s)=_LPF2(s) ω(s),

where,

ω(s)=L(d{^tan−1(_Vβ(t)/_Vα(t))}dt)

L is the Laplace operator. In addition, any change in ∆ω update the value of ω_ff, and the frequency error is removed rapidly under wide frequency deviations. Therefore, the PI controller minimizes the error and therefore the monitoring time is reduced considerably. 4. Performance Analysis of FPLL

The performance and stability analysis is carried out under wide variation in change in frequency and input voltage magnitude. To analyze the stability, the input voltage magnitude is varied from 1 p.u. to 0 p.u. From (6), the FPLL characteristics polynomial is given by

^s3+_ωp ^s2+V_{KP ωp}s+V_{KI ωp}=0

Stability requirements for Routh–Hurwitz refer to the characteristic polynomial equation of the FPLL and the stability conditions are derived as

_ωp>0_KI>0V>0_τi>_τf}

4.1. Evaluation of System Performance under Voltage Sag

The error transfer function (i.e.,_θe(s)/θ(s)) of FPLL is obtained from the small-signal model is

_Ge(s)=_θe(s)θ(s)=^s3s3+_cn2 ^s2+_Vcn1s+_Vcn0

The denominator polynomial is compared to the third order under the damped system in Equation (12).

(s+a)(^s2+2ξ_ωns+_ωn2)

where_ωn—natural frequency of oscillation andξis the damping ratio.

The under-damped third-order system roots are determined by the following PLL parameters

^a3−^a2 _cn2+_aVcn1−_Vcn0=0

The value of the natural oscillation frequency_ωnis identified by taking positive real root,

_ωn’=_Vcn0a

The damping ratio (ξ) of FPLL is determined by

ξFPLL=c_n2−a2_ωn

_θe(t)=_K1 ^e−at+_K2 ^e−_ζωntcos(_ωd+θ)

The Equation (17) indicates that error in theta, where theta is depends on the real pole (a) and complex pole (ξω_n). The ramp reduction of input voltage magnitude results in the raise of the magnitude of ‘a’ and reduction in the magnitude of ξω_n. Table 1 shows the change overshoot and damping ratio for variation in input voltage. Figure 4a shows the change in the magnitude of input voltage, which results in a decrease in the transient response of the system due to an increase in magnitude (‘a’). For different bandwidths, the settling time of FPLLs, increase gradually and remain stable. Figure 4b shows the theta error for a step-change in frequency, from Figure 4b, it is observed that the increase in damping ratio reduces the transients of proposed FPLL with fewer steady-state errors when compared to the conventional system.

4.2. Adaptive Feed-Forward Phase-Locked Loop

In the earlier analysis of the method presented in [20], the FIR filter was considered as a first-order low pass filter to verify the stability of PLL. In this section, the filtering characteristic of the FIR filter is analyzed under a wide variation in input voltage. If any voltage unbalances occur at a nominal frequency, then a ripple of double the fundamental frequency appears in the q_d axis. These ripples result in the erroneous estimation of ‘θ’. However, a low pass filter is used to filter out the ripples, the response time of the system increases. To overcome that, a linear phase FIR filter is added to FPLL, which provides high attenuation to multiple fundamental frequency components.

It is observed that, apart from increasing the dynamic performance of the system, the FIR filter attenuation factor is high during the presence of multiple of the fundamental frequency. However, in FPLL, the FIR filter is designed to operate for a fixed frequency of 50 Hz [20]. This filter effectively eliminates the double frequency ripples under distorted conditions. When the supply frequency deviates from the nominal value, the frequency of the ripples (due to distortions in the grid) also varies with the supply frequency. Hence a filter designed for nominal frequency shows poor performance under frequency variation. In order to overcome this problem, an adaptive FIR filter which updates its parameters for change in supply frequency is proposed. Figure 2 shows the block diagram of the FPLL with an adaptive FIR filter. The FIR filter is designed to remove the distortions in the rotating frame and generate a pure sinusoidal reference signal. It provides a high attenuation during any variation in supply frequency. To solve this problem, an FIR adaptive filter needs this updates its parameter with reference to the change in frequency. The proposed PLL, with an adaptive feed-forward FIR filter, is shown in Figure 2. In this proposed work, the FIR filter coefficient is modified by using a lookup table. The filter coefficients for the frequency range of 20 to 60 Hz are pre-loaded in the lookup table. The frequency variation is divided into 14 bands, which have a 3 Hz bandwidth. Reduction of bandwidth can boost the precision, and it increases the computational burden of adaptive filters. Therefore a bandwidth of 3 Hz is selected with sufficient accuracy. For every change of 3 Hz, the coefficient of the FIR filter is updated with new values from the pre-loaded lookup table. Hence, the adaptive FIR filter updates the coefficients within the specified band, which results in enhanced filtering characteristics under distorted conditions. The filtering characteristics of PLLs are presented in Figure 5 to show effectiveness.

Figure 5a shows the bode magnitude of FPLL in which the filter provides high attenuation at 50, 100, and 300 Hz. The ripple frequency varies with supply frequency if the utility frequency changes. From Figure 5b, it is notable that the Adaptive FIR filter provides high attenuation under frequency variation. When the frequency changes from 50 to 49 Hz, the ripple frequency also changes to multiple of the fundamental frequency, i.e., 98, 147 Hz, etc. it updates the loop filter parameter automatically based on input frequency, which enables to filter out the multiples of the fundamental frequency.

5. Results and Discussion

The simulation of the proposed frequency adaptive feed-forward PLL is simulated using MATLAB/Simulink, and the laboratory prototype is developed for a 3-ϕ, 415 V, 50 Hz source using an Altera Cyclone II field-programmable gate array (FPGA) board. In addition, the laboratory prototype of FPLL is developed to assess the results obtained using the simulation. The developed prototype is shown in Figure 6.

For the development of a prototype, a three-phase IGBT based inverter is built using Semikron Modules. The IGBT is driven by the Semikron SKHI22A gate driver circuit with the switching frequency of 20 kHz. To measure the voltage and current of the inverter and grid, LV25P voltage transducer and LA55P current transducer are used. The control algorithm is digitally implemented using the Altera Cyclone II FPGA board. The grid voltage is adjusted using 3 phase autotransformer to set the required grid voltage. The computer and FPGA board are connected via a USB port to dump the program. To verify the effectiveness of the PLL, the correlation was made between the performance of traditional synchronous reference frame PLL with the performance of proposed adaptive FPLL under phase angle tracking and the wide variation in nominal frequency under abnormal grid conditions such as frequency variance imbalance, phase jump due to addition inductive or capacitive load, harmonics and the relevant results are presented here. The proposed FPLL implemented using a simulation environment has been implemented, and results were obtained under various conditions such as (i) frequency deviation, (ii) phase jump, (iii) harmonics, (iv) unbalance condition. Similarly, the same conditions were incorporated in the developed prototype, and a result obtained via the developed prototype is compared with the simulation studies and other conventional techniques. 5.1. Frequency Deviation

To verify the effectiveness of the PLLs, the system is verified under a dynamic change in input frequency. The input voltage is maintained as constant, and at time t = 0.2 s a step change in frequency is applied to both proposed and conventional systems. The step frequency response of the traditional synchronous reference frame PLL and the proposed adaptive feed-forward PLL for ramp frequency change is shown in Figure 7. Figure 7 shows that the input supply frequency is initially 50 Hz. Both SRF and FPLL signals are in phase with the input signal. At time t = 0.2 s, the step-change in input frequency from 50 to 40 Hz occurs for both SRF and FPLL, and the results (Figure 7a) that SRF PLL exhibits poor performance under frequency deviations when the supply frequency is reduced from 50 to 40 Hz. The SRF PLL is unable to decrease phase and frequency error to zero. This results in a phase lag between the voltage being applied and output theta of PLL. To eliminate the frequency error in FPLL, the gain of the frequency adaptive filter is dynamically varied with the help of a feed-forward frequency loop. The FPLL output is always synchronized with the input signal irrespective of the input frequency deviation from nominal frequency, which is clearly illustrated from Figure 7b.

The performance of SRF PLL and the proposed adaptive feed-forward PLL under a wide change in frequency is depicted in Figure 8. From Figure 8, it is observed that SRF PLL performance is unsatisfactory due to constant feed-forward frequency whereas, in FPLL with adaptive filter, there is a dynamical change in the feed-forward frequency due to the deviations in the supply frequency which quickly eliminates the frequency error. This helps to improve the dynamic response of the FPLL.

Figure 9 shows the performance of the proposed PLL under ramp change in frequency. To evaluate the performance of the PLL’s under distorted supply with ramp change in frequency, the phase voltage is reduced to 0.7V_a at time t = 0.16 s (Figure 9a) and at t = 0.18 s the supply frequency is reduced to 40 Hz. Figure 9a shows the output proposed PLL where the output theta locks the utility within 0.04 s. The performance of the FPLL with a highly distorted input signal is depicting in Figure 9b. In this condition also the input signal in 0.04 s is tracked by the FPLL with a frequency adaptive filter.

Figure 9c shows the phase error simulation response for ramp change in supply frequency from 50 to 40 Hz at t = 0.2 s and Figure 9d illustrates the experimental results for ramp change in frequency. In FPLL, when the frequency changes from 50 to 40 Hz, the Vq component show ripples with a high magnitude, which is illustrated clearly in Figure 9c. In FPLL with a frequency adaptive filter, the steady-state error is reduced to negligible value. This has been verified experimentally and is shown in Figure 9d. To verify the performance under highly distorted conditions, the supply frequency is increased to 40 Hz from 50 Hz at time t = 0.2 s. As seen from the results shown in Figure 9e and Figure 9f, the presence of frequency adaptive filter has considerably increased the FPLL performance by reducing the theta error.

5.2. Phase Jump

The phase jump is the second condition, which is considered to show the effectiveness of the proposed PLL. In this condition, the sudden turning ON/OFF of inductive/capacitive load or a fault in the grid creates a change in phase of the load terminal voltage. To verify the effectiveness of the FPLL with a frequency adaptive filter under this situation, a phase shift of 30° is created with a 30% voltage sag is applied to the ‘A’ phase at time of t = 0.5 s. The simulation and experimental response of the adaptive FPLL (Figure 10a,b) illustrates the effectiveness of the proposed PLL under phase jump. FPLL with frequency adaptive filter locks to input supply and results in an undistorted synchronization signal (cosθ) is formed, which can be observed from the waveforms.

5.3. Harmonics

The performance of FPLL with a frequency adaptive filter with harmonic input is tested by measuring the input current of a 3-ϕ uncontrolled diode bridge rectifier. Because of the presence of multiple of the fundamental frequency (5th and 7th order) in the input signal, the q_d axes have a ripple of 300 Hz. The occurrence of 300 Hz in q_d axis is highly attenuated by FPLL with a frequency adaptive filter, and the system performance is shown in Figure 11a,b.

5.4. Unbalance Condition

To identify the effectiveness of the system, the FPLL with frequency adaptive filter is tested under voltage unbalance condition. For instance, the system is allowed to be in balanced condition and at t = 0.2 s, a sag in voltage of 30% is applied to phase ‘A’. The FPLL with a frequency adaptive filter removes the double frequency ripple and provides a perfect theta under unbalance condition, as shown in Figure 12a. To verify the effectiveness, again, the input three-phase supply is allowed to be in unbalanced condition with a voltage of 30% to phase ‘A’ and at time t = 0.4 s, the three-phase supply is a change to balance condition as shown in Figure 12c. It is observed from the experimental waveforms in Figure 12b,d that the FPLL with an adaptive frequency filter is immune to an unbalance in the input voltage.

5.5. Performance Comparison of PLLs

To show the effectiveness of the proposed PLL, a comparison has been made between the conventional and proposed adaptive feed-forward PLL and shown in Figure 13. The PLL’s performance is tested under different grid abnormalities such as unbalance, harmonics, voltage sag, and frequency deviations. From Figure 13b, it is observed that filtering characteristics of the proposed adaptive feed-forward PLL has improved when compared to the conventional PLL (Figure 13a). The proposed PLL is always stable under any change in voltage magnitude because the system is independent of voltage magnitude.

6. Conclusions An adaptive PLL for tracking of the input signal of phase and frequency under wide frequency variations was presented in this paper. In the proposed system, the center frequency of the PLL is dynamically varied with respect to the supply using a feed-forward loop, which results in the improved dynamic response under wide frequency deviations. The detailed analysis of adaptive feed-forward PLL shows that this feed-forward loop not only improves the dynamic response but also it increases the stability region, and also it reduces the effect of voltage variation on the performance of the FPLL. The filtering characteristics are improved by employing a frequency adaptive filter which filters out the multiple frequency ripples caused by the distorted utility. Further, the proposed adaptive feed-forward loop provides a high attenuation to harmonics yields good filtering characteristics under grid imperfection. The comparison is made with the performance of the proposed PLL and that of the conventional PLL under various grid conditions, and the stability analysis is carried out. The simulation of the proposed frequency adaptive FPLL is simulated using MATLAB/Simulink, and the laboratory prototype is developed to test the PLLs in real-time using an Altera Cyclone II FPGA board. The results obtained for the various grid conditions, such as frequency variation, harmonics, imbalance, and phase shift, illustrate the good filtering characteristics and phase tracking capability of the proposed technique.

Figure 1. Grid-connected photovoltaic system (a) basic block diagram, (b) structure of phase-locked loop (PLL).

Figure 2. Structure of adaptive feed-forward frequency phase-locked loop (FPLL).

Figure 3. Small signal model of FPLL.

Figure 4. Theta Error (a) for a change in input voltage, (b) for step change in frequency.

Figure 5. Filtering characteristics of PLLs. (a) Conventional FPLL [20], (b) proposed adaptive feed-forward PLL.

Figure 6. Prototype of proposed PLL.

Figure 7. Response for frequency changeover from 50 to 40 Hz: (a) cos θ of SRF PLL, (b) cos θ of FPLL with frequency adaptive filter output.

Figure 8. Feed-forward frequency under frequency deviation.

Figure 9. Theta error for frequency during frequency change over from 50 to 40 Hz: (a) cos θ for voltage sag in 'a' phase, (b) cos θ for distorted input signal, (c) phase error under voltage sag-simulation results, and (d) phase error under voltage sag-experimental results, (e) phase error under highly distorted input-simulation results, (f) phase error under highly distorted input-experimental results.

Figure 9. Theta error for frequency during frequency change over from 50 to 40 Hz: (a) cos θ for voltage sag in 'a' phase, (b) cos θ for distorted input signal, (c) phase error under voltage sag-simulation results, and (d) phase error under voltage sag-experimental results, (e) phase error under highly distorted input-simulation results, (f) phase error under highly distorted input-experimental results.

Figure 10. The response of adaptive FPLL: (a) Simulation response under 30°, phase shift and (b) experimental results under 30° phase shift.

Figure 11. The response of adaptive FPLL under harmonic input: (a) Simulation response for 5th and 7th order harmonic input and (b) experimental results for 5th and 7th order harmonic input.

Figure 12. Response of PLL under unbalanced condition: (a) 3-φ balanced input to 3-φ unbalanced input (simulation), (b) 3-φ balanced input to 3-φ unbalanced input (experimental), (c) 3-φ unbalanced input to 3-φ balanced input (simulation), and (d) 3-φunbalanced input to 3-φbalanced input (experimental).

Figure 13. System phase error, (a) conventional PLL [20], (b) adaptive feed-forward PLL.

System	Conventional PLL	FPLL	Conventional PLL	FPLL	Conventional PLL	FPLL	Conventional PLL	FPLL
Voltage	1.p.u.		0.5.p.u.		0.23.p.u.		0.2.p.i.
Closed loop Pole	−28.52 −34 + j73.5 −34 − j73.5	−28.52 −34 + j73.5 −34 − j73.5	−25.49 −11.4−j59.5 −11.4 + j59.5	−48.81 −23.6 + j36.8 −23.6 − j36.8	−22.05 0.155−j36.8 0.155 + j36.8	−78.79 −8.98 + j21.6 −8.98 + j21.6	−21.43 1.01 + j41.6 1.01 + j41.6	−81.44 −7.66 + j20 −7.66 − j20
Damping ratio	0.42	0.42	0.189	0.539	0.0035	0.385	−0.0242	0.357
Overshoot	23.3	23.5	54.6	13.4	98.9	27	108	30.1

Author Contributions

A.C.K.: Conceptualization, Methodology, Software, Data curation, Formal analysis, Writing-Reviewing and Editing. J.P.: Software, Investigation, analysis, Writing-Reviewing and Editing, Supervision. A.S.: analysis, Writing-Reviewing and Editing. T.S.B.: Formal analysis, Visualization, Writing- Reviewing and Editing, Project Administration. M.R.I.: Reviewing and Editing, Project Administration. All authors have read and agreed to the published version of the manuscript.

Funding

This research received no external funding.

Conflicts of Interest

The authors declare no conflict of interest.

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