Analysis and Compensation of the AM-AM and AM-PM Distortion for CMOS Cascode Class-E Power Amplifier

Abstract

Analysis and compensation methodology of the AM-AM and AM-PM distortion of cascode class-E power amplifiers are presented. A physical-based model is proposed to illustrate that the nonlinear capacitance and transconductance cause the AM-AM and AM-PM distortion when modulating the supply voltage of the PA. A novel methodology that can reduce the distortion is also proposed. By degenerating common-gate transistor into a resistor, the constant equivalent impedance is obtained so that the AM-AM and AM-PM distortion is compensated. An experimental prototype of 2.6 GHz cascode class-E power amplifier with the AM-AM and AM-PM compensation has been integrated in a 0.18 μ m CMOS technology, occupies a total die area of 1.6 ^mm2 . It achieves a drain efficiency of 17.8% and a power-added efficiency of 16.6% while delivering 12 dBm of linear output power and drawing 31 mA from a 1.8 V supply. Finally, a co-simulation result demonstrated that, when the distortion of the PA has been compensated, the EVM is improved from -17 dB to -19 dB with an IEEE802.11a-like signal source.

Wen An Tsou 1 and Wen Shen Wuen 1 and Tzu Yi Yang 2 and Kuei Ann Wen 1

Recommended by Liang-Hung Lu

1, Department of Electronics Engineering, National Chiao Tung University, 1001 Ta Hsueh Road, Hsinchu 30010, Taiwan
2, SOC Technology Center, ITRI, 195 Section, 4 Chung Hsing Road, Chutung, Hsinchu 30040, Taiwan

Received 1 September 2009; Revised 19 November 2009; Accepted 12 December 2009

1. Introduction

To increase the data rate, recent wireless communication systems allow the carried information encoded in both amplitude and phase of the RF signal and therefore a linear power amplifier (PA) is required. The linearity achieved in such amplifiers by operating below their maximum output power has the drawback of low efficiency and hence reduced battery lifetime. The switching class-E amplifier is a potential candidate for power amplification in wireless transceivers [1]. However, the PA nonlinearity, the AM-AM and AM-PM distortion, causes the amplitude error and phase error on the output signal and then will severely degrade the emission performance of the system. As discussed in [2], the phase distortion in the class-E power amplifier should be less than the maximum accepted value (5°) in the OFDM-based transmitters.

For highly integrated transceivers, many researches have been focused on the switching class-E PA [3-7], by far the most efficient because hard switching operation and zero voltage switching (ZVS) conditions allow a strong reduction of power losses [7]. In CMOS, switching class-E amplifiers have been integrated with great success since a CMOS technology basically is a digital technology. Unfortunately, class-E amplifiers feature high peak voltages and currents, that seriously stress MOS devices, severely threatening circuit functionality. Moreover, device stacking, in class-E-based PAs, is a viable way to reduce the voltage swing on each device for reliability issues [8]. Cascode class-E PAs are allowed for reliability considerations. However, the linearity problem of the AM-AM and AM-PM distortion during supply modulation is the other design challenge to be concerned.

After identifying the main sources of the distortion in a cascode class-E PA in Section 2, this paper gives insights in the mechanisms of the distortion peculiar of a solution based on the cascode topology and proposed a design methodology for minimizing this distortion, in Section 3. Section 4 describes a design of 0.18 μ m CMOS solution, comprising a class-E power amplifier and a self-biased control circuit. Experimental results are also presented in Section 5. Results of a system cosimulation are compared in Section 6. Finally, Section 7 draws conclusions.

2. Class-E PA Design

2.1. Basic Principle

In class-E PA, the voltage-current separation for efficiency enhancement is obtained by using a tuned LC network. The switch is closed at the instant where both the switch voltage and its first derivative are zero. The requirement of a zero first derivation makes the amplifier less sensitive to component variations. This leads to the well-known class-E conditions as stated by N. O. Sokal and A. D. Sokal [9]:

[figure omitted; refer to PDF] where _t1 represents the instant at which the switch closes, and _vswing (_t1 ) represents the switching voltage.

Figure 1 depicts a circuit that can satisfy the class-E requirements, provided that the correct component values are chosen. If the nMOS transistor is driven by a square wave, it can be viewed as a voltage controlled switch with a nonzero on-resistance _Ron . The lowpass matching network made of _Lm and _Cm transforms 50 Ω , representative of the antenna resistance, into a lower value _Req . The value of _Req is chosen to deliver a desired amount of power with a specific supply voltage _VDD . This network acting as a filter also rejects the harmonics of the class-E waveform at the drain of the nMOS switch. In the original class-E design of Sokal, the RF-choke (_Lck ) is made very large so it acts as a current source. _Cs and _Ls form a series resonator tuned at the desired frequency. Since the class-E working conditions are given by two equations, two components of the circuit can be chosen in such a way that the amplifier fulfills the class-E working conditions. For the circuit of Figure 1, these two components are the capacitor _Cp and the inductor _Lx . In this way, all components are determined.

Figure 1: Schematic of common-source class-E PA.

[figure omitted; refer to PDF]

2.2. Cascode-Based Topology

Regarding gate-oxide breakdown which occurs, if high voltages drop across the gate oxide, deserves particular care in a conventional common-source class-E PA [10]. Due to the class-E operation, the peak drain voltage when the device is off can be as large as 3.56 times the DC supply value [11]. For reliability issues, some efforts had been made to break up with the cascode solution, depicted in Figure 2 [6, 12-14].

Figure 2: Schematic of CMOS cascode class-E PA.

[figure omitted; refer to PDF]

An additional device (_M2 ) is placed in series with the switching device (_M1 ). In this way, the peak _VDS voltage is divided between the two devices and the maximum oxide voltage drop is reduced.

In general, from the reliability standpoint, the bias voltage _VG of the common-gate transistor is specified by the _VDD supply. For highly integration, an RF-choke is replaced by a small dc-feed. However, in practice, _M1 has a finite on-resistance and the transition time from the off-state to the on-state. These factors cause a certain amount of power dissipation on the switch, resulting in a reduction in power efficiency [15].

2.3. AM-AM and AM-PM Distortion

The AM-AM distortion is the difference between the supply voltage and the envelope of the RF output voltage. Such a difference is caused by a nonlinear relationship between the supply voltage and the envelope of the RF output signal. The AM-AM distortion in the RF PA itself can be kept low if it is always operated as a switching amplifier. In other words, the supply voltage of the PA driver stage will be kept high to ensure the switching nature of the amplifier. Besides the AM-AM, the AM-PM distortion will also be presented in the circuit. This distortion is an unwanted phase modulation of the RF output carrier due to the modulation of the supply voltage.

When modulating the PA supply, different operating regions of the transistor _M2 produce a nonlinear capacitance and a transconductance. These nonlinear components cause the AM-AM and AM-PM distortion at the output signal. The model is illustrated in Figure 3.

Figure 3: Equivalent model of the transistor _M2 .

[figure omitted; refer to PDF]

In small supply _VDD , _M2 operates in the deep-triode region and occupies extremely small voltage _VDS2 . When _VDD is large enough to turn _M1 completely on, _M2 can be used for current driving and obtaining a significant voltage headroom _VDS2 . According to the statement above, the voltage _VDS2 is expressed as

[figure omitted; refer to PDF] where _VDD,peak =1.8 V, _Vc =(_VG -_Vth )/λ and λ is the ratio of the maximum peak-drain voltage of _M2 to _VDD,peak . Besides, the capacitance _Cdb2 and transconductance _gm2 of _M2 can be given by

[figure omitted; refer to PDF] [figure omitted; refer to PDF] where _Vbi is the built-in potential of the body diode, _Cj0 is the output capacitance as _VDS2 =0 , and _VGS2 is gate-to-source voltage of _M2 . Equations (2) show that the variations of the _VDD supply caused a nonlinear voltage _VDS2 . In (4), the voltage _VGS2 can also be expressed as _VG -(_VDD -_VDS2 ) . Combining (2)-(4), the relationship of _Cdb2 and _gm2 against _VDD is plotted in Figure 4. The result indicates that the varied _VDD supply causes the nonconstant capacitance _Cdb2 and the nonconstant tranconductance _gm2 .

Figure 4: Theoretical results of _Cdb2 and _gm2 .

[figure omitted; refer to PDF]

To illustrate the AM-AM and AM-PM distortion, the impedance |_Zds2 | at the carrier frequency is derived according to the equivalent model and has been given by (5).

[figure omitted; refer to PDF] where _Cgd2 and _ωo denote the gate-to-drain capacitance of _M2 and angular frequency, respectively. To validate this analysis, the circuit performance was simulated by Agilent ADS simulator, assuming a 0.18 μ m CMOS technology and the following parameter values: _VDD =1.8 V, _ωo =2π·2.6 Grad/sec, _Lck =2 nH, _Cs =5 pF, _Cm =0.9 pF, _{(W/L)M1 ,M2} =(1080/0.18) μ m/μ m, and the totally inductance of _Ls , _Lx , and _Lm is 2.9 nH. The simulated and theoretical results of |_Zds2 | are compared in Figure 5. The theoretical result is in good agreement with the simulated result and also indicates that the variant capacitance and the transconductance of _M2 bring a nonconstant |_Zds2 | . The difference between the theoretical result and the simulated result is due to the saturation voltage of transistors and the voltage drops of _Lck are neglected. Furthermore, the output drain voltage waveform of _M2 suffers from the magnitude and phase errors due to the nonconstant impedance. The PA output signal accompanies with the magnitude and phase errors from the drain node, so-called the AM-AM and AM-PM distortion. The simulated result of the AM-AM and AM-PM distortion is shown in Figure 6.

Figure 5: Theoretical and simulated result of |_Zds2 | and _VDS2 against supply voltage.

[figure omitted; refer to PDF]

Figure 6: AM-AM and AM-PM distortion.

[figure omitted; refer to PDF]

The result reveals that the relationship of the envelope of the RF output voltage against the supply _VDD is nonlinear and the voltage deviation at _VDD =0 V causes an additional distortion at low envelope levels. When the supply voltage of the amplifier deviates from its optimum value (1.8 V), maximum AM-PM changes by 21 degrees/V and 18° of the phase error down to 0.5 V. In the supply voltage of 0 V to 0.5 V, the AM-PM is highly nonlinear and the phase error is as large as 67°. These characteristics indicate that low envelope levels are harder to reconstruct than high envelope levels.

3. Compensation Methodology

3.1. Improved AM-AM and AM-PM

Since various impedances will cause the nonlinear effect, a constant |_Zds2 | should be designed to compensate this distortion. To obtain a constant |_Zds2 | , one of design solutions is to force the transistor _M2 to act as a resistor. When the common-gate transistor has been operated as a resistor, it is expected that the nonlinear capacitance and transconductance should be canceled. This requirement is realized by a voltage adder, as shown in Figure 7.

Figure 7: Equivalent schematic of the PA when the PA with AM-AM and AM-PM compensation.

[figure omitted; refer to PDF]

In Figure 7, the adder produces a voltage, which equals the threshold voltage _Vth plus the supply _VDD , on the gate node of _M2 and therefore _M2 will be operated as a triode-mode resistor. During supply modulation the output voltage of the adder varied with the supply _VDD always forces _M2 to operate as a triode-mode resistor while _M1 is a switch. Therefore, a constant |_Zds2 | is obtained and its simulated result is shown in Figure 8. The result shows that the voltage _VDS2 is linearized and hence a constant |_Zds2 | is obtained.

Figure 8: Simulated |_Zds2 | and _VDS2 against supply voltage when the PA with compensation.

[figure omitted; refer to PDF]

The results of the PA with and without the AM-AM and AM-PM compensation are compared in Figure 9. When the PA has the compensation, the relationship of the envelope of the output voltage against the supply voltage is linear and the AM-PM in the supply voltage of 0.5 V to 1.8 V is improved from 18° to 3°. Therefore, the proposed methodology evidently has compensated the AM-AM and AM-PM distortion of the PA during supply modulation.

Figure 9: Compared AM-AM and AM-PM distortion.

[figure omitted; refer to PDF]

3.2. Efficiency Analysis

One more advantage of the transistor _M2 operating as a resistor is to pull up drain efficiency in low supply voltage and extend the operating supply range. The DC current (_IDC ) in [16] can be rewritten by (6), where _Vdmin means the finite drain-to-source voltage during the transistor conducting and _Rs is the source terminal resistance. Drain efficiency of the PA can be expressed by (7). When the PA with or without the proposed compensation methodology is operating on the identical conditions of _Pout and _VDD , drain efficiency is inversely proportion to _IDC :

[figure omitted; refer to PDF] [figure omitted; refer to PDF]

Figure 10 shows the results of _IDC and drain efficiency versus the supply voltage. In small supply voltage, the _IDC value of the PA with compensation is less than the PA without compensation and therefore drain efficiency of the PA is increased. The maximum improvement of 15% is achieved at _VDD =0.65 V. This improvement benefits the operation of the PA in low supply voltage. In other words, the proposed methodology can extend the operating supply range during supply modulation since the PA has the slightly degradation in drain efficiency in high supply voltage. The results of power gain and output power against the supply voltage are also reported in Figure 11, where the input driving power is 6 dBm. When the amplifier is compensated, the power gain and output power of the PA are not degraded. The result indicates that the AM-AM and AM-PM distortion of the class-E power amplifier is compensated without degrading the circuit performance.

Figure 10: Compared DC current and drain efficiency.

[figure omitted; refer to PDF]

Figure 11: Gain and output power against supply voltage.

[figure omitted; refer to PDF]

4. Implementation

A fully integrated cascode class-E power amplifier with a self-biased control circuit for compensating the AM-AM and AM-PM distortion has been implemented in a 0.18 μ m CMOS technology, as shown in Figure 12. The amplifier operates at 2.6 GHz from a 1.8 V supply voltage and, to obtain the expected voltage _Vco , the self-biased control circuit is applied by 3.3 V supply voltage. The 50 Ω load resistance is downconverted by means of the _Lm -_Cm network. The series of _La -_Ca are implemented to improve power efficiency [8]. A way to minimize the power loss is to tune out the capacitive parasitics by the inductor _La , resonating parasitic capacitances on node P at the desired frequency of operation. A blocking capacitor _Ca is inserted between the inductor _La and ground. For highly integration, all of passive devices are implemented by the internal components. Considering the electrical performance of internal inductors, they have an allowed current density of 1 mA/μ m at the temperature of 85°C and internal inductors have a maximum metal width of 20 μ m, a thickness of 2 μ m. Therefore, avoiding the metal damage of _Lck , the PA was designed to have an allowed current capacity. Hence, the large output power and drain efficiency are not the major design targets in this amplifier. The aspect sizes of the transistor _M1 and _M2 are 1080/0.18 μ m/μ m.

Figure 12: Detailed schematic of proposed PA.

[figure omitted; refer to PDF]

The self-biased control circuit tends to produce a voltage, the sum of a DC voltage and an analogue voltage. It is implemented by a voltage adder, including an operating amplifier with several resistors. Selecting the ratio of resistors, the expected output voltage is obtained. Besides, the operating amplifier has the unit-gain frequency of 100 MHz for achieving a correct output voltage of the self-biased control circuit during supply modulation. The control circuit is just to produce a gate biasing voltage of _M2 , so that it only draws few micro amperes from the 3.3 V supply.

5. Experimental Results

Fabricated prototypes have been measured by the probe testing. The chip photomicrograph is reported in Figure 13. Total die area is 1.6 mm². Figure 14 shows the measured characteristics of the AM-AM and AM-PM of the PA. The phase error is reduced down to 5° as _VDD is swept from 0.7 V to 1.8 V. A linear voltage relationship is also obtained and there is a small deviation in low supply voltage, from 0 V to 0.3 V. As expected, the AM-AM and AM-PM distortion of the class-E PA has been compensated by using proposed design methodology. The prototype delivers an output power of 12 dBm with a 1.8 V supply voltage and an input driving power _PIN of 6 dBm. The output power can be regulated by changing the supply voltage of the amplifier. Figure 15 shows the measured output power (_POUT ), drain efficiency (DE), and power-added efficiency (PAE) versus _VDD . Drain and power-added efficiencies are defined as follows [17, 18]:

Figure 13: Die photo.

[figure omitted; refer to PDF]

Figure 14: Measured AM-AM and AM-PM effect.

[figure omitted; refer to PDF]

Figure 15: Measured output power (_POUT ), PAE, and drain efficiency (DE) versus _VDD .

[figure omitted; refer to PDF]

[figure omitted; refer to PDF] where _PDC-BIAS and _PDC-PA are the power drawn from the supply by the control circuit and PA stage, respectively.

The output power increases proportionally to ^{_VDD 2} , varying from -2 dBm to 12 dBm, as _VDD is swept from 0.3 V to 1.8 V. In small supply voltage, the transistors can not be completely on so that the amplifications of the RF signal are not available. Drain efficiencies are close to 20% in _VDD of 0.5 V to 1.8 V. As the supply voltage below 0.6 V, the PAE has seriously reductions, whereas the PAE reduces when the output power becomes comparable to the input power. Due to the targeted output power reduced from 16 dBm to 12 dBm, the maximum PAE is also reduced to 16.6%. The output power and power gain versus the input power are also reported in Figure 16. The PA has the output power of 12 dBm and power gain of 6 dB with an input driving power of 6 dBm. When _PIN is above 7 dBm, the power gain of the PA is degraded to 5 dB. The result of the output power versus frequency is shown in Figure 17. The output power is above 12 dBm in the 2.3 GHz to 2.8 GHz frequency band, leading the power amplifier to operate in a wide frequency band. The maximum PAE in this wide frequency band is 23.5%.

Figure 16: Measured output power and power gain versus input power.

[figure omitted; refer to PDF]

Figure 17: Measured output power and PAE versus frequency.

[figure omitted; refer to PDF]

The design proposed here shows that the AM-AM and AM-PM distortion of the cascode class-E PA has been compensated by a self-biased control circuit without dissipating more power. However, because of the concern of an allowed current capacity on the top metal layer, the aspect sizes of the transistors for efficiency optimization are difficult to achieve. Therefore, the equivalent series resistances of the transistor are large when the transistor is on, so that there is reduction on the drain voltage waveform and the output power. Due to the reduction of the output power, the efficiency of the amplifier is also reduced.

6. System Verification

A system cosimulation platform of envelope elimination and restoration (EER) architecture shown in Figure 18 was established to determine the influence of the AM-AM and AM-PM distortion of the cascode class-E PA on system performance. The signal source, an IEEE802.11a-like broadband OFDM transmission with 20 MHz bandwidth and operating at a 2.6 GHz frequency, is generated by an ADS Ptolemy simulator. The histogram of envelope voltage in Figure 19 shows that 93% of envelope voltages are in the range from 0.5 V to 1.8 V with a mean voltage of 1 V, while the request time delay is 2.8 nanoseconds [19]. Using the distortion compensation technique of the cascode class-E PA, the EVM can be improved from -17 dB to -19 dB, and the obtained constellation is shown in Figure 20.

Figure 18: System cosimulation platform of EER.

[figure omitted; refer to PDF]

Figure 19: Histogram of the envelope voltage.

[figure omitted; refer to PDF]

Obtained constellations (a) without compensation and (b) with compensation.

(a) [figure omitted; refer to PDF]

(b) [figure omitted; refer to PDF]

All of results have been summarized on Table 1. It shows that the proposed methodology can effectively compensate the distortion of the PA while the measurement result is also in good agreement with the simulation result.

Table 1: Performance summary.

	Simulation	Cosimulation	Measurement
	(AM-PM)	(AM-PM)
w/o compensation	18°	EVM = -17 dB	N/A
(0.5 V-1.8 V)
w/i compensation	3°	EVM = -19 dB	5°
(0.5 V-1.8 V)	(0.7 V-1.8 V)

7. Conclusions

A cascode class-E PA with a self-biased circuit has been proposed in this paper to achieve the reduction of the AM-AM and AM-PM distortion. We carefully investigated the distortion in cascode class-E PAs, finding that an equivalent triode-resistor by the common-gate transistor is a way to cancel the nonlinear capacitance and the transconductance for the reduction of the AM-AM and AM-PM distortion. A simplified equivalent model is introduced to illustrate the mechanisms of the distortion. Furthermore, a design methodology for compensating this distortion has been identified and a circuit solution has also been proposed. The prototype of 2.6 GHz class-E amplifier, realized in a 0.18 μ m CMOS technology, has demonstrated that the phase error is reduced down to 5° in the supply voltage of 0.7 V to 1.8 V and the output power of 12 dBm over the 2.3 GHz to 2.8 GHz frequency band from a 1.8 V supply voltage. The EVM of an EER on a system cosimulation is improved from -17 dB to -19 dB.

Acknowledgments

This work was conducted by the Trans-Wireless Technology Laboratory (TWT Lab.) and sponsored jointly by the Ministry of Education and the National Science Council, Taiwan. The authors would like to thank Dr. K. W. Huang of National Nano-Device Laboratory (NDL), Taiwan, for chip testing.

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