Computation in the context of transport triggered architectures

Abstract

Processors used in embedded systems have specific requirements that are not always met by off-the-shelf processors. A templated processor architecture, which can easily be tuned toward a certain application (domain) offers a solution. The transport triggered architecture (TTA) templated presented in this paper has a number of properties that make it very suitable for embedded systems design. Key to its success is to give the compiler more control; it has to schedule all data transports within the processor. This paper highlights two important TTA-related issues. First, a new code generation method for TTAs is discussed. Second, how to tune the instruction repertoire for an embedded processor is discussed.