Design of Low-Power 10-Transistor Full Adder Using GDI Technique for Energy-Efficient Arithmetic Applications

Abstract

The general focus of this work is to design an area-optimised full adder and utilise it to lay out a low-power arithmetic unit that can be helpful for microprocessors. A traditional full adder with 28 transistors has been devised with 10 transistors of an equal amount of PMOS and NMOS, guaranteeing the proper switching activity. The proposed full adder has one XOR gate and two 2:1 multiplexers in which the XOR gate has been customised with 4 transistors using pass transistor logic (PTL). In contrast, the gate diffusion input (GDI) technique has been used to alter the multiplexer design. The combination of the GDI and PTL brings a novelty to the full adder circuit, through which the design required only 10 transistors to perform adding operations. The proposed full adder design has been constructed against ten different complementary metal oxide semiconductor processing technologies, namely 0.6 µm, 0.8 µm, 0.12 µm, 1.2 µm, 0.18 µm, 0.25 µm, 0.35 µm, 50 nm, 70 nm and 90 nm. Pre- and post-layout simulations evidence the accuracy of the results in which the design consumes 1.843 µW of power with 0.605 ns as the worst-case delay on 90 nm technology. Further, the full adder has been extended as an adder/subtractor unit of 4 bits, with the power delay product as 0.1285 × 10^− 18 J for the critical delay of 1.095 ns. The proposed design has been compared against the various full and approximate adders. The full adder has a 12.99% power reduction over the existing low-power adder and a 58.4% power reduction over the 28 transistors. This ensures that the proposed adder outperforms the traditional design and the state of the artwork.