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Recommended by S. Nikolaidis and G. Snider
Department of Electronics and Communication Engineering, Motilal Nehru National Institute of Technology, Allahabad 211004, India
Received 15 November 2012; Accepted 4 December 2012
This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
1. Introduction
During the past decade, use of adiabatic logic circuits with energy recovery scheme has received considerable attention in high performance low-power applications such as radio-frequency identification (RFID) tags, smart cards, and sensors because they outperforms in energy efficiency without sacrificing noise immunity and driving ability over their CMOS counterparts. The power consumption in conventional CMOS circuits is proportional to the load capacitance and square of the supply voltage [ 1, 2], thus researchers have been focused on scaling of the supply voltage and reducing the capacitance to reduce power consumption. For scaling the supply voltage the transistor threshold voltage ( V t ) must also be scaled down proportionally, however reducing the transistor threshold voltage V t results in proportional increase in subthreshold leakage current. Further the circuit capacitance can be minimized by reducing the sizes of devices but this affects the driving ability of the circuit [ 3].
Due to the above limitations, in recent years adiabatic systems have been used to reduce power consumption. Various adiabatic logic circuits have been proposed [ 3- 21] working on the energy recovery [ 4] principle. The term "adiabatic" is derived from a reversible thermodynamic process [ 5] and it stands for a system where a transformation takes place in such a way that no gain or loss of heat/energy occurs. Ideally the heat/energy loss can be made almost zero if the transformation takes place sufficiently slowly [ 6]. The main idea in an adiabatic charging is that transitions are considered to be sufficiently slow so that all the nodes are charged or discharged at a constant current. In this way power dissipation is minimized by decreasing the peak current flow [ 7] through the transistors. This is made possible by replacing the DC power source by ramp like power/clock signals [ 8, 9]. The energy that is stored in the capacitors during charging...