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ABSTRACT
This paper presents a different approach of the Rijndael-AES symmetric algorithm, based on the addition of Mix Columns transformation, which originally belongs to the AES standard algorithm, before/after/before&after the Rijndael-AES encryption/decryption block and to the secret encryption/decryption key, resulting a new symmetric algorithm, in 3 different versions (M -AES, AES-M, M -AES-M), which the author of this paper generically called the AES PLUS algorithm. This paper also presents some aspects regarding the hardware (FPGA) implementation of the standard and proposed algorithms. The NIST statistical tests both applied to the AES-128 algorithm and to the new one proved that the M -AES-M version has a better statistical behavior than the original AES-128 standard algorithm.
Keywords: Rijndael-AES symmetric algorithm, MixColumns transformation, hardware (FPGA) implementation, statistical tests.
1. INTRODUCTION
The specifications for the Rijndael-Advanced Encryption Standard (AES) symmetric algorithm, as [1] and [2], stipulate a final encryption/decryption round without its most complex transformation, that is the Mix Columns transformation. This is a finite field (Galois Field (2^sup 8^)) multiplication between the data block (organized in 4x4 binary matrix, with 8 bit numeric coefficients, which is called State) and a constant matrix operand (e.g. in case of the AES- 128 version of the standard algorithm, organized in 4x4 binary matrix, with 8 bit constant coefficients). The author of this paper did not find any explanation for this fact, so he had the idea to add the missing transformation before/after/before& after the Rijndael-AES encryption/decryption block, together with the same transformation of the secret encryption/decryption key, resulting a new symmetric algorithm, in 3 different versions (M -AES, AES-M, M -AES-M), which the author of this paper generically called the AES PLUS algorithm.
This paper also presents the hardware (FPGA) implementations of the standard and of the proposed algorithm, all in iterative loop configurations, which will provide conesponding cryptographic modules.
Finally, the resulted cryptographic modules are statistically tested, using a special designed FPGA test unit and the NIST statistical test suite.
The improved algorithm (AES- 128 PLUS), that is the modified AES- 128 version of AES, will be presented, but the other versions of AES can be similarly modified.
2. A DIFFERENT ARCHITECTURAL APPROACH
The architecture of the AES block encryption/decryption algorithm contains, as shown in Fig. 2.1, an initial...