Effects of Equivalent-Oxide-Thickness and Fin-Width Scaling on In0.53Ga0.47As Tri-Gate Metal-Oxide-Semiconductor-Field-Effect-Transistors with Al2O3/HfO2 for Low-Power Logic Applications

Abstract

We created tri-gate sub-100 nm In_0.53Ga_0.47As metal-oxide-semiconductor-field-effect-transistors (MOSFETs) with a bi-layer Al₂O₃/HfO₂ gate stack and investigated the scaling effects on equivalent-oxide-thickness (EOT) and fin-width (W_fin) at gate lengths of sub-100 nm. For L_g = 60 nm In_0.53Ga_0.47As tri-gate MOSFETs, EOT and W_fin scaling were effective for improving electrostatic immunities such as subthreshold swing and drain-induced-barrier-lowering. Reliability characterization for In_0.53Ga_0.47As Tri-Gate MOSFETs using constant-voltage-stress (CVS) at 300K demonstrates slightly worse V_T degradation compared to planar InGaAs MOSFET with the same gate stack and EOT. This is due to the effects of both of the etched fin’s sidewall interfaces.

1. Introduction

Traditional SiO₂/Si-based gate stack downscaling has approached its fundamental and applied limits due to high current density leakage through ultrathin SiO₂ and the material limitations of Si. This impacts the Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) operating speed, reliability, condensed device density, and power consumption. Indium-rich In_xGa_1−xAs channel materials, where x > 0.53, are the most promising non-Si n-channel candidates for next-generation Complementary-MOS (CMOS) technology at and beyond the 5-nm technology node. The most promising new technology is a combination of a high-k oxide and III-V channel materials because of outstanding carrier transport properties such as the effective electron mobility (µ_n) and injection velocity (ν_x0) [1,2,3,4,5,6]. For the past three decades, a key bottleneck in developing III-V MOSFETs has been poor interface state quality between the oxide and III-V channel [7,8,9,10,11]. Atomic-layer-deposition (ALD) provides a very good quality interface, presumably due to the “self-cleaning effect” during the high-k deposition, especially in the In_0.53Ga_0.47As channel [12,13,14,15]. The high-k gate dielectric can reduce leakage current through a thick physical dimension while keeping an equivalent oxide thickness (EOT). Recently, using the ALD process, our group demonstrated a tri-gate In_0.53Ga_0.47As MOSFET and an ultra-thin-body (UTB) planar InGaAs MOSFET with high-k gate stacks. This indicated an excellent interface trap density (D_it) [16]. Among the high-k dielectrics Al₂O₃, HfO₂, La₂O₃, ZrO₂ and TiO₂ oxides that have been studied, no single dielectric is a clear leading contender. However, both Al₂O₃ and HfO₂ are quite attractive due to the ease of fabrication using the ALD process. Even though Al₂O₃ has a comparatively large bandgap (~8.8 eV), a good interfacial boundary with a self-cleaning effect, high thermal stability, fewer active electrical defects and a moderate dielectric constant (k = 6–9). Conversely, even though HfO₂ has a higher dielectric constant (k = 20–25) and moderate bandgap (~5.7 eV), it has lower thermal and interfacial stabilities, larger hysteresis, a higher leakage tendency, and more active electrical traps. Using this information, we created an InGaAs MOSFET with Al₂O₃/HfO₂ bi-layer gate stack scaled down to an EOT below 1 nm [16,17]. The UTB planar InGaAs MOSFET with Al₂O₃/HfO₂ exhibits outstanding performance parameters, including S = 69 mV/dec, DIBL < 10 mV/V, C-V hysteresis < 10 mV/V with D_it = 2.7 × 10¹² /cm²-eV and EOT ≈ 0.7 nm [16,17].

For a deeply scaled-down transistor using 5-nm technology, body thickness (t_body) has to be thinned down in such a way that L_g can maintain electrostatic immunity. However, thinning down t_body degrades the carrier transport and increases parasitic resistance in the channel. A non-planar structure with a tri-gate configuration is an effective way to improve electrostatic immunity while preserving the carrier transport’s ability to maintain parasitic resistance [18,19].

In this paper, we address the benefits of EOT and fin-width scaling on subthreshold swing and DIBL in tri-gate InGaAs MOSFETs. We also demonstrate preliminary reliability characterization to verify the etched fin’s sidewall interface and damages when the devices are in operation mode.

2. Materials and Methods

The device fabrication process started with a conventional sequence of mesa isolation with H₃PO₄-based wet chemistry to isolate the current path. Non-alloyed Mo-based ohmic contact for S/D was evaporated on top of a heavily doped InGaAs cap layer. This was followed by two E-beam lithography steps consisting of fin formation for non-planar structures. Next, the gate was recessed to expose an area for the high-k gate stack. This was done utilizing wet-based chemistry. Two types of high-k, Al₂O₃/HfO₂ (0.7 nm/1.6 nm) and Al₂O₃ (3 nm), were deposited to split the EOT. Their corresponding EOTs were ≈ 0.7 nm for Al₂O₃/HfO₂ (0.7 nm/1.6 nm) and ≈ 2 nm for Al₂O₃ (3 nm). ALD-based 20-nm TiN was deposited for the metal-gate (MG). The process flow was conducted below 350 °C to avoid any thermal damage to the gate region. The completed tri-gate InGaAs MOSFET had an L_g = 60 nm, 20 nm fin-height (H_fin), and fin-width (W_fin) range from 60 nm to 30 nm. The effective gate-width (W_{g_eff}) was calculated using the equation W_fin + 2 × H_fin. A planar type InGaAs MOSFET was also made with an ultra-thin-body (5 nm) and Al₂O₃/HfO₂ (0.7 nm/1.6 nm) gate stack. Figure 1 shows the conceptual architecture of the 3D tri-gate In_0.53Ga_0.47As MOSFET and a cross-sectional schematic of each fin along the gate-length direction. We also made a MOS capacitor on top of the InGaAs surface to optimize the interface trap.

Figure 2 shows the corresponding C–V_GS measurement at V_DS = 0 V for a planar MOSFET with Al₂O₃ (left) and Al₂O₃/HfO₂ (right) from 10 kHz to 1 MHz. Both C–V_GS curves exhibit small frequency dispersion in a strong accumulation region. The hump near the off-state is a consequence of D_it. Inset is the C–V_G from MOSCAPs with the same gate stacks, where EOT is extracted to 2 nm for the Al₂O₃ gate stack and 0.7 nm for the Al₂O₃/HfO₂ gate stack. For the planar MOSFET with the Al₂O₃/HfO₂ gate stack, the gate capacitance is 15.5 fF/μm² at V_GS–V_T = 0.5 V, the highest for any MOSFETs.

From C–V_GS and I_D–V_GS at the linear bias regime (V_DS = 0.05 V) for planar MOSFETs, effective mobility (μ_eff) can be determined. Even with an EOT of sub-1nm, the planar InGaAs MOSFET yields a μ_eff in excess of 3000 cm²/V-s at 300 K. This is 5 times higher than Si universal mobility reported in the literature [20].

3. Results and Discussion

Figure 3 shows the subthreshold characteristics of L_g = 60 nm tri-gate InGaAs MOSFET with different values of EOT and W_fin. Figure 3a depicts EOT scaling from 2 nm to 0.7 nm with W_fin = 60 nm. EOT = 0.7 nm, with S = 94 mV/dec. and DIBL = 40 mV/V, is better than EOT = 2 nm, where S = 104 mV/dec. and DIBL = 54 mV/V. Figure 3b depicts W_fin scaling from 60 nm to 30 nm with EOT = 0.7 nm. This highlights how W_fin scaling improves the electrostatic integrity in tri-gate InGaAs MOSFET devices. When EOT = 0.7 nm, the device with W_fin = 30 nm shows an improvement of S and DIBL (S = 77 mV/dec. and DIBL = 10 mV/V) compared to W_fin = 60 nm (S = 94 mV/dec. and DIBL = 40 mV/V). The inset shows S as a function of V_gs.

Figure 4 shows a comparison between the subthreshold characteristics of the tri-gate MOSFET with L_g = 60 nm, W_fin = 30 nm and the ultra-thin-body (UTB) planar MOSFET with L_g = 50 nm. The UTB planar MOSFET was reported previously and has a similar physical gate length [21]. The tri-gate InGaAs MOSFET shows a much sharper subthreshold swing and less DIBL at the measured regime. This means the tri-gate MOSFET provides better electrostatics and higher values of ON-current (I_ON) than the planar MOSFET with a similar physical gate length.

To investigate the plasma-etched sidewall fin surfaces, we conducted a reliability characterization of the planar InGaAs MOSFET and non-planar tri-gate InGaAs MOSFET using constant-voltage-stress (CVS) at 300 K. Figure 5 shows that V_T shifts as a function of stress time under CVS iterations and relaxes at 300 K for the tri-gate and planar MOSFETs. The tri-gate MOSFET shows slightly more V_T degradation than the planar MOSFET. At 2000 s of stress time, the tri-gate MOSFET shows a shift in ΔV_T of 90 mV at V_G–V_T = 1.25 V, presumably due to the effect of the sidewall interface from the etched fin. Further surface cleaning processes such as high-pressure annealing (HPA) will help improve the etched surface after the fin etching process.

4. Conclusions

We investigated the effect of EOT and W_fin on the electrostatic integrity of tri-gate InGaAs MOSFETs at gate lengths in the sub-100 nm regime. EOT and W_fin scaling help to improve the short-channel effects. In addition, reliability characterization for InGaAs tri-Gate MOSFETs using constant-voltage-stress (CVS) at 300 K revealed slightly more V_T degradation compared to planar InGaAs MOSFETs with the same gate stack and EOT. This indicates that the etched fin effect on both sidewall interfaces is not a concern for the etched tri-gate process.

Author Contributions

T.-W.K. conducted most of the experiments, wrote the manuscript, initiated the work, and supervised the process. Author has read and agreed to the published version of the manuscript.

Funding

This research was supported by Civil-Military Technology Cooperation Program (No. 19-CM-BD-05).

Conflicts of Interest

The authors declare no conflict of interest.

Figures

Figure 1. (a) Tri-gate InGaAs Quantum-Well (QW) MOSFET architecture. Bi-layer high-k (HK) gate dielectric stacks with Al2O3/HfO2 were used, followed by ALD-based TiN deposition. Fin geometry is 20 nm fin-height (Hfin) and fin-width (Wfin) ranging from 60 nm to 30 nm. (b) Cross-sectional schematics of each fin along the gate-length direction are shown in (b). This is equivalent to SOI Tri-gate MOSFET architecture.

Figure 2. C–VGS measurement at VDS = 0 V for planar MOSFETs with Al2O3 (left) and Al2O3/HfO2 (right) from 10 kHz to 1 MHz. Inset is C–VG from MOSCAP with same gate stacks. Both C–VGS curves show small frequency dispersion in strong accumulation regions, the hump near off-state is a consequence of Dit. For devices with Al2O3/HfO2 gate stacks, Cg is 15.5 fF/μm2 (VGS–VT =0.5 V), the highest in any of the MOSFETs.

Figure 3. Subthreshold characteristics comparison of Lg = 60 nm tri-gate InGaAs MOSFET depending on Wfin and EOT scaling. (a) EOT scaling at Wfin = 60 nm and (b) Wfin scaling at EOT = 0.7 nm.

Figure 4. Benchmarks of subthreshold characteristics for both Lg = 60 nm tri-gate InGaAs MOSFET and Lg = 50 nm UTB planar MOSFET.

Figure 5. VT shift as a function of stress time under iterations of (a) CVS (Constant-Voltage-Stress) and (b) relaxation at 300K for tri-gate and planar MOSFETs.