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This paper provides a detailed description of the IBM SiGe BiCMOS and rf CMOS technologies. The technologies provide high-performance SiGe heterojunction bipolar transistors (HBTs) combined with advanced CMOS technology and a variety of passive devices critical for realizing an integrated mixed-signal system-on-a-chip (SoC). The paper reviews the process development and integration methodology, presents the device characteristics, and shows how the development and device selection were geared toward usage in mixed-signal IC development.
1. Introduction
Silicon-germanium (SiGe) BiCMOS technology, which achieved its first manufacturing qualification in 1996, is now in its fourth lithographic generation of development. This class of technology integrates high-performance heterojunction bipolar transistors (HBTs) with state-of-the-art CMOS technology. Key technology characteristics for the four generations have been reported by IBM [1-4]. All generations of BiCMOS technology are compatible with an associated IBM CMOS technology in devices, metallization (interconnects), and ASIC design system. Figure 1 is a SiGe BiCMOS chart showing the evolution of performance and minimum lithographic feature size together with some derivative technologies. As shown in Figure 2, the HBT cutoff frequency [function of]^sub T^ has improved from 47 GHz in the 0.5-[mu]m generation to 210 GHz in the 0.13-[mu]m generation. The pace of development continues unabated, and there are no apparent barriers to scaling the SiGe HBTs beyond 210 GHz.
The SiGe HBT performance has been significantly improved by a combination of vertical and lateral scaling. Structural improvements included shrinking the emitter width and reducing layer thicknesses for the first three generations and migrating to a new raised extrinsic base (RXB) structure for the 0.13-[mu]m generation. Vertical profile scaling included increasing the drift field by increasing the Ge concentration and reducing the graded base width, adding carbon (C) to decrease diffusion, reducing the thickness of the collector epitaxial layer, and minimizing the emitter thermal cycle. In the 0.13-[mu]m generation, vertical and lateral profile scaling has led to a reduction in the parasitics of the HBT, especially in the base, collector, and emitter resistances (R^sub B^, R^sub C^, R^sub E^) and total collector-base capacitance (C^sub CB^). Coupled with the increased [function of]^sub T^, this reduction in parasitics is expected to lead to an increased [function of]^sub max^ (the maximum frequency of oscillation of a device, often referred to as U, for unilateral...