Generalized Circuit Averaging Technique for Two-Switch PWM DC-DC Converters in CCM

Abstract

Design of DC-DC converters like Cuk and SEPIC, which are fourth-order converters, play a vital role in the design of electric vehicle (EV) charging systems and drivers for LED. These converters possess a unique feature of input current being continuous due to the presence of an inductor in series with the supply voltage. In the present work, a generalized approach for obtaining the frequency response of the transfer function of the duty cycle to output voltage (G_vd) for converters operating in continuous conduction mode (CCM) having two switches is proposed. A practical Cuk converter and SEPIC operating in CCM were selected and their analyses in open loop were studied using the LTSpice simulation tool. The behavior of the output voltage and inductor currents under variable ESR’s (equivalent series resistance) of inductors was studied. It was observed that G_vd of these converters was unstable. Hence, an appropriate controller to stabilize the system and achieve a proper gain margin and phase margin in closed-loop operation is required.

1. Introduction

The control of DC-DC converters is essential to achieve regulated voltage and current. There are several methods for obtaining the open-loop transfer functions viz., small signal modeling, circuit averaging, and state space averaging. The ideal converters show noticeable deviations from the practical converters in terms of stability due to ESR in the capacitor. In the past, several attempts have been made in determining the transfer functions of G_vd and input voltage to output voltage (G_vg) for several complex converters using different methods. Small signal modeling and state space averaging are some of the techniques employed for obtaining the open loop response for converters like Buck, Boost, and Buck-Boost. These methods become laborious when the order of the converter increases. Hence, a simpler method, circuit averaging, was introduced to the Cuk converter and Single Ended Primary Converter (SEPIC) [1]. In [2,3], a mathematical model for Cuk was presented. The importance of selecting a proper step size in MATLAB/Simulink was highlighted. The closed-loop operation for obtaining constant output voltage was simulated. In [4], the circuit averaging for the Cuk converter was carried out using a Saber circuit simulator, and G_vd and G_vg were found out theoretically and verified using simulation. G_vd showed complex pole conjugates and G_vg showed a right half plane (RHP) zero. In [5], circuit averaging using LTSpice for basic converters during ideal conditions was analyzed. However, the simulation and analysis for non-ideal higher-order converters was not carried out. In [6], the modeling of switching DC-DC converters was shown using state space modeling including parasitic values considering switching and conduction losses. In [7], a state space modeling approach for a fourth-order converter using MATLAB / Simulink was shown.

Circuit averaging is applied to Buck, Boost, Buck-Boost, and Cuk converters operating in CCM and the non-idealities like inductor and capacitor ESRs are included [8]. However, the non-idealities in the diode and the MOSFET were not considered.

A generalized technique for a non-ideal Cuk and SEPIC converter operating in CCM and DCM is shown in [9]. The model was simulated using LTSpice and the converter selected its operation based on the value of the duty cycle.

In any DC-DC converter, the switching losses are higher than the conduction losses [1]. The switching loss for a two-switch PWM converter is modeled as a resistor. Hence, the switching power loss can be incorporated into existing averaged small-signal dynamic models in basic converters operating in CCM [10]. To determine the value of the switching loss resistor component, an energy balance equation was used. A SEPIC operating in DCM was selected to drive a light-emitting diode (LED) for constant voltage application [11]. An average and a switching model were developed, modeled in MATLAB/Simulink, and validated against the experimental results. The transfer functions G_vd and G_vg were derived. It was shown that the SEPIC provided lower input current harmonics. An ideal SEPIC and Cuk operating in DCM were selected and used for power factor correction (PFC) [12]. The input to the converters was supplied by a single-phase rectifier. The open-loop transfer function obtained using the small signal model was validated against the hardware results and they were found to be closely correlated. The concept of circuit averaging for converters like Buck, Boost, and Buck-Boost in DCM was discussed [13]. It was shown that the input and output ports of such converters behave like a resistive and power sink, respectively.

In this paper, averaged models for non-ideal fourth-order converters like Cuk and SEPIC operating in CCM is analyzed using the LTSpice simulation tool. In earlier works, the dynamics of the converters considering the non-idealities using the circuit averaging technique were not presented for specific converters like Cuk and SEPIC. The equations required to model the switch network are shown in detail in this paper. The behavior in the output voltage under a variable inductor ESR was also studied. The modeling approach is generic and hence can be applied to a DC-DC converter of any order operating in CCM having MOSFET and diode. Circuit averaging is an advanced technique to determine G_vd using an averaged switch network. This technique involves less computation (switch voltages and currents) to determine the frequency response of G_vd and is recommended when the converter contains more than one inductor and capacitor. G_vd obtained from circuit averaging matches with that obtained from the state space model. 2. Circuit Averaging for an Ideal SEPIC

Figure 1 shows an ideal SEPIC with MOSFET and a diode. The voltages and currents are denoted as V₁, V₂, I₁, and I₂, respectively. Figure 2 shows the converter with the switches separated.

Circuit averaging of any converter involves three major steps viz.:

• Separate the switch network from the converter and define the ports.
• Sketch the waveform of the switch current and voltage waveforms and average it.
• Simplify the equations and draw the equivalent switch network.

Averaging V₁, V₂, I₁, and I₂ waveforms:

⟨V1⟩=(1−d)(Vc1+Vc2)

⟨V2⟩=d(Vc1+Vc2)

⟨I1⟩=d(iL1+iL2)

⟨I2⟩=(1−d)(iL1+iL2)

From (1) and (2), eliminating (Vc1 + Vc2):

Vc1+Vc2=V1d=V21−d

Vc2=V1∗d1−d

Similarly, from (3) and (4), eliminating (iL1 + iL2):

I1=I2∗d1−d

From (7) and (8), the turns ratio for the transformer can be derived as:

M=V2V1=N2N1=D1−D

Equations (7) and (8) represent the generalized equations applicable to any switch PWM converter operating in CCM having two switches. 3. Small Signal Model The small signal model provides the AC equivalent circuit in which the non-linear equations are linearized. V₁, V₂, I₁, and I₂ derived are now perturbed.

Perturbing (6):

(^d′−d^)(V2+V2^)=(d+d^)(V1+V1^)

where^d′=1−d.

Similarly, perturbing (7):

(^d′−d^)(I1+I1^)=(d+d^)(I2+I2^)

Figure 3 shows the equivalent large signal DC/AC switch model.

4. Circuit Averaging for a Non-Ideal SEPIC

Figure 4 shows the non-ideal SEPIC with V₀ = Vc2.

⟨V1⟩=d(Ron1∗(iL1+iL2))+^d′((Vc1+Vc2)+Vd+Rd(iL1+iL2))

⟨V2⟩=d((Vc1+Vc2)−Ron1(iL1+iL2))+^d′(Vd+Rd(iL1+iL2))

⟨I1⟩=d(iL1+iL2)

⟨I2⟩=^d′(iL1+iL2)

Simplifying (13) and (14):

I1d=I21−d

From (12):

Vc1+Vc2=V2d+Ron1∗(iL1+iL2)d−^d′(Vd+Rd∗(iL1+iL2))

Substituting (16) in (11) and upon simplification:

V2=I1Ron1d+(1−dd)∗(V2+Vd+Rd∗I1d)

The equivalent circuit for (18) is shown in Figure 5.

5. Circuit Averaging for a Non-Ideal Cuk

Figure 6 shows an ideal Cuk converter operating in CCM. Figure 7 shows the MOSFET and diode separated from the converter.

Figure 8 shows the waveforms of switch voltages and currents at dT_s and (1 − d)T_s intervals, which is similar to Figure 9.

⟨V1⟩=Vc1∗(1−d)

⟨V2⟩=dVc1

⟨I1⟩=d∗(iL1+iL2)

⟨I2⟩=(1−d)∗(iL1+iL2)

Eliminating Vc1:

V11−d=V2d

V2=(V1∗d)/^d′

The turns ratio of the transformer irrespective of the converter would remain the same, i.e.:

M=N2N1=V2V1=D1−D

Therefore, the equivalent circuit would remain the same as that of the SEPIC. 6. Circuit Averaging for Non-Ideal Cuk Converter

On averaging the voltages and currents across the switches:

⟨V1⟩=d(Ron1∗(iL1+iL2))+^d′(Vc1+Vd+Rd∗(iL1+iL2))

⟨V2⟩=d(Vc1−Ron1∗(iL1+iL2))−^d′(Vd+Rd∗(iL1+iL2))

⟨I1⟩=d(iL1+iL2)

⟨I2⟩=^d′(iL1+iL2)

Eliminating iL1 and iL2:

I1d=I2d

From (25):

Vc1=V2d∗Ron1∗I1d+1−dd∗(Vd+Rd∗I1d)

Substituting (29) in (24):

V1=I1∗Ron1d+1−dd∗(Vd+Rd∗I1d)

The small signal is generic and provides results for any DC-DC converter having two switches operating in CCM. 7. Converter Specifications

Table 1 shows the specifications of Non-ideal Cuk converter.

Table 2 shows the specifications of Non-ideal SEPIC.

8. Results Simulations were performed using LTSpice software. The equivalent switch network was available as a built-in library under ‘average.lib’ library.

D was varied from 0.3 to 0.6 every 1 ms and the corresponding iL1 and V₀ were analyzed. Figure 10 and Figure 11 show the variation of iL1 and V₀ with respect to the D for Cuk and SEPIC, respectively. It was observed that an increase in D caused an increase in iL1. However, V₀ for Cuk and SEPIC increased in the negative and positive directions, respectively.

In Figure 12, R_L was varied from 0.1 Ω to 0.3 Ω in steps of 0.1. It was observed that higher R_L provided higher iL1 and V₀. SEPIC also showed similar features. In Figure 13, R_L1 and R_L2 were varied. It was found that the lowest value of R_L1 and the highest value of R_L2 provided higher voltage levels.

Figure 14 shows the Bode plot of G_vd for an SEPIC under the variation of D from 0.2 to 0.9 in steps of 0.01 considering a fixed load. The crossover frequency was about 4.207 kHz, gain cross over frequency about 169.45 kHz, gain margin about −43.60 dB, and phase margin about −30°. Thus, the open loop behavior of SEPIC is unstable. A step change in R varying from 80 Ω to 100 Ω in steps of 10 Ω was simulated. As shown from Figure 15, a higher value of R created higher resonance.

Similar to that of SEPIC, D was varied from 0.2 to 0.9 in steps of 0.01 for a non-ideal Cuk converter. The cross-over frequency was about 2.92 kHz with a gain margin and phase margin of about −23.85 dB and −160.894°, respectively. Thus, the open-loop system was unstable. Figure 16 shows a bode plot of G_vd for a fixed value of R. A similar feature in G_vd for varying R was seen in the practical Cuk converter shown in Figure 17. G_vd was computed in LTSpice software using the AC sweep command.

The frequency response of G_vd obtained from the circuit averaging and small signal model for a non-ideal Cuk converter was compared. The specifications shown in [3] were chosen, simulated, and compared. Figure 18 shows the circuit averaging model for the selected converter using the LTSpice software tool. Figure 19 shows G_vd obtained from the circuit averaging technique using the AC sweep command. Figure 20 and Figure 21 show the G_vd plots based on [3].

It can be observed that G_vd obtained from circuit averaging and [4] closely match.

9. Conclusions The circuit averaging technique for fourth-order converters like Cuk and SEPIC was carried out using the LTSpice software tool. This generalized approach to predict the frequency response of G_vd can be applied for any two-switch PWM DC-DC converters operating in CCM. This method is comparatively simple and easy to implement compared to the conventional small signal and state space averaged models. The lowest value of R_L1 and the highest value of R_L2 cause higher voltage levels. G_vd becomes unstable in the open-loop configuration for the chosen converters. This technique does not provide the transfer function equation of G_vd. However, the specifications like gain and phase margins and gain and phase cross-over frequencies can be easily found and its stability can be analyzed. The LTSpice model was used for the two-switch configuration in this paper. However, it can be extended to converters having multiple switches.

Figure 1. Circuit diagram.

Figure 2. Separate the switches.

Figure 3. Equivalent switch network, where {1} isd^V1d∗d'and {2} isI2d^d∗d'.

Figure 4. Switches separated.

Figure 5. Equivalent switch circuit.

Figure 6. Circuit diagram.

Figure 7. Switches separated.

Figure 8. Waveforms during switch ON and OFF conditions.

Figure 9. Waveforms during Switch ON and OFF conditions, where {1} and {2} are Vc1 + Vc2 and {3} and {4} are iL1 + iL2.

Figure 10. Variation of iL1 and V0 with change in D (Cuk). (a) Output Voltage Vs. Control Voltage, (b) Inductor 1 Current Vs. Control Voltage

Figure 11. Variation of iL1 and V0 with change in D (SEPIC). (a) Output Voltage Vs. Control Voltage, (b) Inductor 1 Current Vs. Control Voltage

Figure 12. Variation of iL1 and V0 with change in RL (Cuk). (a) Output Voltage Vs. Control Voltage, (b) Inductor 1 Current Vs. Control Voltage

Figure 13. Variation of iL1 and V0 with change in RL (SEPIC). (a) Output Voltage Vs. Control Voltage, (b) Inductor 1 Current Vs. Control Voltage

Figure 14. Gvd for SEPIC for fixed R.

Figure 15. Gvd for SEPIC for variable R.

Figure 16. Gvd for Cuk for variable R.

Figure 17. Gvd for Cuk for variable R.

Figure 18. Circuit averaged model.

Figure 19. Gvd for a non-ideal Cuk converter.

Figure 20. Theoretically derived Gvd for a non-ideal Cuk converter [4].

Figure 21. MATLAB-generated Gvd for a non-ideal Cuk converter [4].

SL.NO	Specifications	Value
1	Input Voltage, Vg	28 V
2	Output Voltage, V0	10 V
3	Output Current, I0	1 A
4	Inductors, L1 and L2	330 µH
5	Inductor ESR, RL1 and RL2	0.1 Ω
6	MOSFET Resistance, Ron1	31 mΩ
7	Duty Cycle, D	0.3
8	Capacitors, C1 and C2	6.8 µH
9	Capacitor ESR, Resr	0.2 Ω
10	Switching Frequency, fs	100 kHz
11	Diode Drop, Vd	0.8 V
12	Diode Forward Resistance	0.8 Ω

SL.NO	Specifications	Value
1	Input Voltage, Vg	300 V
2	Output Voltage, V0	400 V
3	Output Current, I0	5 A
4	Inductors, L1 and L2	2.57 mH & 1.71 mH
5	Inductor ESR, RL1 and RL2	130 mΩ & 110 mΩ
6	MOSFET Resistance, Ron1	321 mΩ
7	Duty Cycle, D	0.571
8	Capacitors, C1 and C2	4.7 µF & 3.57 µF
9	Capacitor ESR, Resr	270 mΩ & 350 mΩ
10	Switching Frequency, fs	100 kHz
11	Diode Drop, Vd	0.62 V
12	Diode Forward Resistance	80 mΩ

Author Contributions

Proposed idea and carried out modeling and simulation, S.S.; Guidance and Advice, S.W. Both authors have read and agreed to the published version of the manuscript.

Funding

This research received no external funding.

Institutional Review Board Statement

Not applicable.

Informed Consent Statement

Not applicable.

Data Availability Statement

Not applicable.

Conflicts of Interest

The authors declare no conflict of interest.

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