High-Drain Field Impacting Channel-Length Modulation Effect for Nano-Node N-Channel FinFETs

Abstract

Three dimensional (3-D) FinFET devices with an ultra-high Si-fin aspect ratio have been developed after integrating a 14Å nitrided gate oxide upon the silicon on insulator (SOI) wafers through an advanced CMOS logic platform. Under the lower gate voltage (V_GS-V_T) and the higher drain/source voltage V_DS, the channel-length modulation (CLM) effect coming from the interaction impact of vertical gate field and horizontal drain field was increased and had to be revised well as the channel length L was decreased. Compared to the 28-nm MOSFETs, the interaction effect from the previous at the tested FinFETs on SOI substrate with the short-channel length L is lower than that at the 28-nm device, which means the interaction severity of both fields for nFinFETs is mitigated, but still necessary to be concerned.

1. Introduction

With the evolution of process technology and the need of marketing, exploring the high speed, low cost, and high-volume capacity in integrated-circuit (IC) chips is the development trend in the modern semiconductor industry [1,2,3]. As the process of technology enters the nano-node generation, seeking the better device structure compatible with the Si-based process flow is a good way to promote the drive current and product competition. The fin field-effect transistor (FinFET) structure is one of the impressive candidates in the tremendous competitive FET devices [4,5,6,7]. In order to obtain ultra-high density metal-oxide-semiconductor FET-like (MOSFET) IC products, a 3D FinFET device has been incorporated as a promising candidate as compared to other double gate device structures [8,9] owing to its process compatibility with conventional logic devices. Furthermore, FinFET devices demonstrate the advantages of avoiding the shallow trench isolation process as well as effective improvement of drive current I_ON, device leakage I_OFF, subthreshold swing, drain-induced barrier lowing (DIBL) effect, and short channel effect (SCE) due to the good controllability of gate electrode surrounding the erected silicon body of Si-fin [10,11]. Besides the substrate with silicon bulk substrate [12,13], the device fabricated by adopting the silicon-on-insulator (SOI) wafer [14,15] in high-performance computing (HPC) products including the advanced 5G/6G communication systems, smart phones, quantum calculation, artificial intelligent applications, and driverless systems are a feasible choice [16,17,18]. Using the SOI wafer, the benefits for IC chips compared with the conventional bulk silicon substrate chiefly contain lower supply power which can reduce power by 2 to 3 times, high performance which reduces switching delays and gains the improvement of 20% to 30% in speed, soft error rate and radiation hard reduced because the FET devices are isolated from substrate [19,20]. Moreover, HPC products adopting FinFET devices usually operate at the high-frequency or microwave range [21,22], the complication of IC design is increased more, including the noise issue [23,24].

Consequently, besides the improvement of physical process development, the precise simulators for IC design houses are indeed necessary to make sure IC production is successful because each investment of nano-node IC products is over a couple million US dollars or more. With the accurate sets of intellectual property (IP), the successful rate in IC design is possible and hugely raised. Hence, providing a set of accurate device models bridging the foundry and the design houses in the nano-node era with fin-Si structure is an important contribution. Due to this effort, in addition to promoting the drive current [25] and indirectly increasing the operation speed, the reliable device models consolidating the process and device simulation software will enhance the stability of circuit operation. In the past, some researchers studied the device model with early voltage [26,27,28,29] causing from the channel-length modulation effect at the 28-nm process technology with traditional bulk wafers. However, the device model is chiefly focused on the higher vertical field at the gate electrode. The model of the early effect under the low-field operation was not described well. To compensate this insufficiency, this study will entirely probe the early effect on the single-fin and multi-fin FinFETs with some various channel-length devices, as shown in Figure 1. Adopting the multi-fin FinFETs to possibly reduce series resistance and source/drain-to-gate capacitance, the source/drain current I_DS is also increased more, but not unlimited and linearly increased with the increase of fin number [30,31,32]. One of the possible causes is that the micro-loading effect in the etching process is more distinct, especially in the high aspect ratio of fin height/fin channel width. The other side effect for the increment of fin number degrades the performance of device reliability such as in the hot-carrier stress [33] because carrier conduction in the steep Si fins of FinFETs is different for a device with multiple number of fins and probably affects device performance and reliability. In general, the unsuitable device models will influence the accuracy of circuit performance in simulation and real operation [34]. Thus, seeking the more accurate device model [35,36] is the main task in this study. In this case, the contours of the tested FinFETs are the channel width/the channel length (W/L) on mask: 0.12/0.10, 0.12/0.24, and 0.12/0.50 (μm/μm) as well as one and eleven fins.

2. Brief Illustration of Device Formation

Designing a set of device layout patterns following the design rules is necessary to probe the accuracy of process flow and device performance, as shown in Figure 2 and Figure 3. Furthermore, the SOI wafers before the definition of the active area were well done in preparation and clean. Continuously, the location and implantation of N/P-well was defined and processed, respectively. With photo-lithography and etch technology, the Si-fin shape was formed. The threshold-voltage implants (V_T implant) for n-channel and p-channel FinFETs [37,38] were executed to determine the adequate V_T values. Applying the photo lithography and etch process, the desired gate patterns with 11-nm channel width under the over-exposure and adequate etch assistant were obtained. The fin height was about 87 nm [39]. The nitrided oxide with the physical thickness 14Å played as a gate oxide was grown [40,41] as a cap oxide. The undoped poly-Si with epitaxy technology of a chemical vapor deposition (CVD) method was deposited on the gate oxide. The source/drain extension (SDE) implants for n/p-FinFETs were followed to form a protection shield against the hot-carrier effect (HCE) [42]. Consequently, the spacer was deposited to the designed thickness. The source/drain (S/D) implants for both type of FinFETs, and beneficial for the poly-gate conduction, were conducted, respectively. On the heels of the anterior process, the cobalt-silicide process [43] was adopted to reduce the contact resistant and avoid the contact spiking.

Continuously, with strain technology processes [44,45] is helpful to the increase of channel mobility. Following the sub-65nm conventional CMOS process until M1 layer, the front-end FinFETs were completely manufactured. In the end, the back-end of line (BEOL) processes [46,47] including the signal connection patterns, passivation deposition, and contact window were step by step followed up to protect the whole devices and extract the electrical characterization of the devices. The simple cross-section of a complementary n/p-channel FinFET is demonstrated in Figure 4. The cross-sectional TEM (transmission electron microscope) photos with single Si-fin under different photo exposure energy are as shown in Figure 5. The top-view SEM (scanning electron microscope) photos for multi Si-fin and single Si-fin are exhibited in Figure 6 and the concise process flow is denoted in Figure 7.

3. Results and Discussion

For an n-channel FinFET (nFinFET), the drive current (I_DS) at the saturation mode can be represented as Equation (1) [28,29]:

_IDS≈_Wt2⋅m⋅L_μnCox^{(_VGS−_VT)2}(1+ΔLL),

where W_t: total channel width = fin channel width + 2 fin height = W_fin + 2 H_fin, L: channel length, m: body effect factor, μ_n: channel mobility, C_ox: gate capacitance per area at the inversion mode, V_GS: gate/source voltage, ∆L: pinch-off region, as shown in Figure 8.

In the past, the ∆L/L was only described to relate the horizontal field V_DS. It could be represented as Equation (2):

ΔLL≈λ_VDS,

where λ is the channel length modulation factor as 1/V_A and V_A is the early voltage.

When we consider the vertical contribution, Equation (2) may be modified as Equation (3):

ΔLL≈λ_VDS+α(_VGS−_VT)+β(_VGS−_VT)_VDS,

where α and β are also the channel length modulation factors related to the vertical field and the mutual-interaction between both, respectively. The effective channel length L’ is defined as (L−∆L).

One of the measured results for the electrical characteristics of the S/D currents vs. V_GS-V_T or V_DS with W/L = 0.12/0.10 (μm/μm) on mask at room temperature is shown in Figure 9. Generally, the multi-fin FinFET is to increase the drive current compared with the single FinFET or 2-D MOSFET due to the multi-channel or the increment of fin height increasing the whole channel gate width and drive current. The intercept voltage operated at each V_GS–V_T indicates the early voltage (V_A). When the vertical field (V_GS–V_T) operated is lower and fixed and the V_DS is higher, Equation (3) can be simplified as ∆L/L ≈ [λ + β(V_GS–V_T)]V_DS, which means the minor contribution of α(V_GS–V_T) is able to be ignored because of comparing the other terms in the right-hand side of Equation (3) in this assumption. For the different channel lengths, the extracted values for λ and β are listed at Table 1Table 2Table 3 and Table 4. The distribution of β-values can be treated as two mechanisms. In Table 1 and Table 2, the vertical field is lower and the β-value linearly plays a slope of 1/V_A vs. (V_GS–V_T), as shown in Figure 10. Reversely, it is higher in Table 3 and Table 4 and the contribution of β-value is hugely reduced. We suggest that when the higher drain and gate fields are applied, the carrier transport mechanism in channel is not pure to be explained with the uniform charge distribution, but includes the quantum mechanical effect [29] and the ballistic transport with Boltzmann distribution [48].

Through the decrease of the channel lengths, the β-factor is increased, especially at the shortest one which means the contribution coming from the vertical field is more distinct [49]. As the establishment of the device models at the short channel part, this vertical effect dominating the accurate model must be of concern more than before. Comparing the extracted consequence for β-factor with Reference 26 (β ≈ 1.4~1.6), the β-factor for the FinFET at the long-channel device is a little higher than that at the 28-nm MOSFETs. As the device channel length is narrowed down, the vertical-field contribution to the drive current is gradually increased, as shown in Figure 10. On the contrary, when the V_DS and the V_GS–V_T are higher, the β-factor at FinFETs with short-channel device is less than that at Reference 26, as shown at Table 3 and Table 4. There is a turning point observed at the L = 0.24 μm, showing the minimum value owing to the bias of photo-lithography. This channel-length modulation should be adjusted and the β-factor must be extracted carefully. For the multi-fin device, the process issues are also possible to influence the electrical performance. For instance, the micro-loading effect for the multi-fin devices in etching process technology is a tremendous challenge, affecting the etching performance and probably causing the expected aspect ratio of fin height/ fin channel width, which cannot be approached. In spite of this, using the β value to justify the etching performance in different multi-fin structures can be treated as an extra benefit in process monitoring. In addition to the foregoing lithography [50] and dry etch [51] impacting the roughness and uniformity of Si-fin strongly correlated to the β-factor, the ion doping factors including the doping energy, doping dosage, and dopant species in adjustment of threshold implantation will probably influence the β-factor. Hence, each novel or changed process flow will follow a new set of device models.

The related electrical characteristics of I_DS vs. V_GS and I_GS vs. V_GS for the tested device with W/L = 0.12/0.1 (μm/μm) are demonstrated in Figure 11 and Figure 12, respectively. The measurement equipment is Keysight B1500A which can provide the accuracy current range until fA (10⁻¹⁵ A) level. The threshold swings (SS) for single and multi-fin FinFETs are 96 and 85 mV/decade, respectively. These electrical performances in device design are acceptable although the SS value for single fin is a little higher, which is still less than 100 mV/decade. Because the SS value is an index to illustrate the capability of ON/OFF speed of FinFETs. As the single and multi-fin FinFETs are scanned by the gate bias, the multi-fin device usually provides more drive current than the single one. Hence, we suggest that the swing capability of the multi-fin device should be better than that of the single one.

Concerning the contribution of plasma etching with micro-loading effect, the main effort focused on the multi-fin contour. The interface integrity of single FinFET on the channel surface has been suffered a little more. The gate leakage in accumulation mode as source/drain grounded is low like noise and in inversion mode is gradually raised up as V_GS is positively increased. The speculation is that because the substrate of tested devices is SOI-type floating, not bulk-type, the channel potential for the tested device is unstable at the accumulation mode. Thus, the gate leakage in measurement is treated as noise. However, as the SOI devices are biased at the inversion mode, the channel potential is grounded with source/drain electrodes. Hence, the pseudo noise issue is reduced more and the gate leakage is truly responding. In the future, the simulator provides not only the simulation functions of process and device, but the reliability functions together. In reliability concern, the electrical performance in devices or IC shifting is 10% in operating or thermal stress is treated as a failed sample. Thus, providing an accurate set of device models is urgently needed at the sub-28-nm node, which can shorten the IC development time, advance the yield of IC products, and save more money in the entire project. 4. Conclusions

Considering the 3-D FinFET device upon SOI wafer with an ultra-thin Si-fin, it is indeed feasible to be employed to deep sub-nano process technology such as the sub-14-nm node [52,53,54]. Before the high-k dielectric integrated into HPC IC products or the low-cost consideration, providing the oxy-nitride (SiON) dielectric as gate dielectric is still an adoptable way to temporarily satisfy the need of IC design houses. In this article, while the FET device is narrowed down, the device model in channel-length modulation becomes more complicated owing to the contribution of the vertical gate field. In these tested FinFETs, we observed that the β-factor illustrating the contribution of the vertical field was increased as the channel length decreased at the higher V_DS and lower V_GS-V_T case. For both at the higher, the trend of the β-factors with the channel lengths were reverse. Using these consequences incorporating into the device model beneficially improving the device performance at the sub-28-nm node is desirably expected. Furthermore, this kind of application in model improvement also can be extended to gate-all-around (GAA) FETs or multi-bridge-channel (MBC) FETs for sub-7-nm manufacturing technology [55,56,57] or other FET-like devices [58].

Figure 1. The scheme of FinFETs with single and multi-fin contours on SOI wafer.

Figure 2. The top-view layout for single FinFET.

Figure 3. The top-view layout for multiple FinFETs.

Figure 4. The cross-sectional profile of a complementary n/p-channel FinFET.

Figure 5. TEM photos for single Si-fin under exposure energy: (a) 28 mJ and (b) 31 mJ.

Figure 6. Top-view of SEM photos: (a) multi Si-fin and (b) single Si-fin.

Figure 7. The simple flow chart of FinFET formation.

Figure 8. The concise cross-sectional contour of an n-channel FinFET.

Figure 9. IDS vs. VDS with W/L=0.12/0.10 (µm/µm): (a) single-fin and (b) multi-fin.

Figure 10. Distribution of (VA)-1 vs. VGS-VT with single-fin and multi-fin. Inset: linear regression at the low vertical gate field and VDS = 1.2 V.

Figure 11. Electrical characteristics of IDS vs. VGS for single and multi-fin n-channel FinFETs as W/L = 0.12/0.1 (μm/μm) at VDS = 0.05 V.

Figure 12. Gate leakage performance for single and multi-fin n-channel FinFETs as W/L = 0.12/0.1 (μm/μm) as S/D grounded.

W/L (μm/μm)	0.12/0.10	0.12/0.24	0.12/0.50
λ	−6.0893	−0.15	−0.5492
β	20.023	0.375	1.7857

W/L(μm/μm)	0.12/0.10	0.12/0.24	0.12/0.50
λ	−9.1018	−0.5778	−0.4222
β	26.632	0.9998	1.1667

W/L(μm/μm)	0.12/0.10	0.12/0.24	0.12/0.50
λ	−0.6019	−0.2611	−0.3319
β	0.3175	0.1667	2.083

W/L(μm/μm)	0.12/0.10	0.12/0.24	0.12/0.50
λ	−1.4767	−0.2897	−4.0787
β	0.7515	0.1190	2.4963

Author Contributions

Conceptualization, M.C.W.; methodology, W.C.H.; formal analysis, C.R.L., W.S.L., and W.S.L.; data curation, W.L.C.; writing-original draft preparation, M.C.W.; writing-review and editing, W.C.H., W.S.L. and W.H.L.; project administration, C.R.L. All authors have read and agreed to the published version of the manuscript.

Funding

This research received no external funding.

Institutional Review Board Statement

The study was conducted according to the guidelines of the Declaration of Helsinki, and approved by the Institutional Review Board.

Informed Consent Statement

Informed consent was obtained from all subjects involved in the study.

Data Availability Statement

Not applicable.

Acknowledgments

The authors sincerely appreciate United Microelectronics Corporation in Taiwan for supporting 8" SOI wafers, and the financial support from Ministry of Science and Technology of Republic of China under Contract Nos. MOST 109-2622-E-159-001.

Conflicts of Interest

The authors declare no conflict of interest.

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