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A linear CMOS power amplifier (PA) is developed for wideband code-division multiple-access (W-CDMA) application using 0.18 µm silicon-on-insulator (SOI) technology. By adopting a quadruple-stacked FET structure, 1W of output power is achieved at 4V supply voltage. A negative capacitance circuit is employed to maximise the efficiency of the PA by cancelling out the excessive capacitance at the source terminal of the common-gate stage. Besides, a lineariser based on the variable capacitor circuit is added to reduce the inherent AM-PM distortion of the CMOS FET. Using W-CDMA modulation at 837MHz, the fabricated PA module delivers a PAE of 47.5% and an adjacent channel leakage ratio of - 36dBc at the output power of 27.1dBm.
Introduction: CMOS technology is promising for single-chip radio integration for cellular mobile terminals. The power amplifier is one key building block that makes full transceiver system integration very difficult. Besides the isolation issues, CMOS transistors suffer from low breakdown voltage and poor linearity owing to relatively large knee voltages [1].
Among various ways, a stacked FET configuration is an attractive option for power combining of low-breakdown voltage devices, where the voltage swing from each FET is added in phase to achieve high output power [1]. By terminating the gates of common-gate (CG) FETs with proper capacitance, the voltage swing can be maintained below the breakdown voltage limits. Even if the breakdown issues are successfully addressed, the poor device linearity remains as an obstacle for 3G/4G linear power applications [2].
In this Letter, a highly efficient watt-level linear CMOS PA is devel- oped using an integrated lineariser in a stacked-FET configuration. A negative capacitance circuit is employed to cancel out the excessive gate capacitance, and a lineariser based on a variable capacitor is added to compensate for large AM-PM distortion of the CMOS FET. The fabricated CMOS PA module shows a PAE of 47.5% with an adja- cent channel leakage ratio (ACLR) of - 36dBc using the W-CDMA signal.
Circuit design: The stacked FET PA is composed of one common- source (CS) FET and multiple CG FETs connected in series, as shown in Fig. 1. Small shunt capacitors (C2, C3, C4) are attached to each gate terminal of the CG-FETs instead of large bypass capacitors for RF-grounding. In this way, the...