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Several technologies are leveraged to establish an architecture for a low-cost, highperformance memory controller and memory system that more than double the effective size of the installed main memory without significant added cost. This architecture is the first of its kind to employ real-time main-memory content compression at a performance competitive with the best the market has to offer. A large low-latency shared cache exists between the processor bus and a content-compressed main memory. High-- speed, low-latency hardware performs real-- time compression and decompression of data traffic between the shared cache and the main memory. Sophisticated memory management hardware dynamically allocates main-memory storage in small sectors to accommodate storing the variable-sized compressed data without the need for "garbage" collection or significant wasted space due to fragmentation. Though the main-memory compression ratio is limited to the range 1:1-64:1, typical ratios range between 2:1 and 6:1, as measured in "real-world" system applications.
Introduction
Memory costs dominate both large memory servers and expansive computation server environments such as those employed in today's "data centers" and "computer farms." These costs are both fiscal and physical (e.g., volume, power, and performance associated with the memory system implementation), and often aggregate to a significant cost constraint that the information technology (IT) professional must trade off against computing goals.
Data compression techniques are employed pervasively throughout the computer industry to increase the overall cost efficiency of storage and communication media. However, despite some experimental work [1, 2], system main-memory compression has not been exploited to its potential. IBM Memory Expansion Technology (MXT*) addresses the system memory cost issue with a new memory system architecture that more than doubles the effective capacity of the installed main memory without significant added cost.
MXT is directly applicable to any computer system, independent of processor architecture or memory device technology. MXT first debuted in the Serverworks "Pinnacle" chip, an Intel Pentium** III/Xeon** bus-- compatible, low-cost single-chip memory controller (Northbridge) [3]. This unique chip is the first commercially available memory controller to employ realtime main-memory content compression at a performance level competitive with those of the market's best products.
Architecture
Conventional "commodity" computer systems typically share a common architecture, in which a collection of processors are connected to a common SDRAM-based main memory through a memory...