Implementation of UART Design for RF Modules Using Different FPGA Technologies

Abstract

This paper is focused on the designing of UART (Universal Asynchronous Receiver Transmitter) for RF based modules, which is a type of serial communication protocol, mainly used for short-distance, low speed and low-cost data transmission between two embedded systems or computer peripherals. These days RF-Microcontroller modules widely uses UART protocol for the interface with other hardware. A reduced FSM (Finite State Machine) UART design has been implemented on different FPGAs. The maximum achievable speed and their corresponding power consumption are calculated using these FPGAs. The proposed design is implemented using Verilog HDL and for simulation purpose, Xilinx ISE 12.1, 14.7, Xilinx Vivado 2018 and Intel Quartus Prime 19.1 are used. The smallest value of maximum power consumption i.e. 20.67mW at 105.47MHz frequency with 180nm technology node is achieved by Intel Max V among all the Intel and Xilinx devices. Furthermore, the maximum achievable frequency i. e. 769.48 Hz has been found in Virtex 4 FPGA device. Xilinx Virtex UltraScale+ devices occupy the minimum area which provides 16-nm FinFET Technology node.