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A low-leakage current, low-area voltage regulator for system-on-a -chip processors is proposed. The system is demonstrated in a 0.13 µm CMOS technology with a supply voltage varied between 0.8 and 1.5 V. Using this system, the leakage current and power are reduced by as much as 44× and 33×, respectively, compared to conventional topologies.
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Introduction: One of the most pervasive trends in digital CMOS IC design is the scaling of transistor dimensions, which has allowed for more integrated designs and reducing of the cost of consumer electronics. This, however, comes at a cost of increased design complexity. In addition to design complexity, scaling the transistor dimensions increases the leakage current per transistor while increasing the number of transistors on-chip. This causes the overall stand-by power of the overall chip to be quite significant.
Conventional method: One method of reducing stand-by power consumption is to cut off the power supply. This is usually implemented using a PFET device to act as a switch between the power supply and the microprocessor, as shown in Fig. 1. The PFET device is sized sufficiently large such that the drop across the PFET device is minimised in active mode, given the maximum expected load. As shown in Fig. 1,if CTRL is high, the switch is enabled. If it is low, it is disabled, and the power supply is cut off from...