Low Power State Retention Technique for CMOS VLSI Design

Abstract

Mobile computing and mobile communication applications, which are powered by battery, the battery life is a major concern. Leakage power dissipation is critical in VLSI circuits, as the battery leaks even when devices are in idle state. To reduce leakage power, as well as total power in CMOS logic gates and circuits, a new circuit technique called LPSR technique is proposed in this paper. Earlier, well known techniques for leakage reduction and state retention are compared with this technique. This technique reduces maximum amount of static leakage power during deep sleep mode, maximum power reduction during dynamic mode and has a provision of preserving state in low power sleep mode. All the circuits are designed, simulated and low power performance evaluation is done using CMOS technology files in Tanner EDA tool.

Headnote

Abstract

Mobile computing and mobile communication applications which are powered by battery, the battery life is a major concern. Leakage power dissipation is critical in VLSI circuits as the battery leaks even when devices are in idle state. To reduce leakage power as well as total power in CMOS logic gates and circuits a new circuit technique called LPSR Technique is proposed in this paper. Earlier well known techniques for leakage reduction and state retention are compared with this technique. This technique reduces maximum amount of static leakage power during deep sleep mode, maximum power reduction during dynamic mode and has a provision of preserving state in low power sleep mode. All the circuits are designed; simulated and low power performance evaluation is done using CMOS technology files in Tanner EDA tool.

Keywords

Power dissipation, leakage currents, static power, state retention.

1. Introduction

Mobile computing and mobile communication applications which are powered by battery, the battery life is a major concern in designing. Leakage power loss is critical in Integrated circuits as it leaks the battery even when devices are in idle state. The on-going technology scaling has resulted in the use of low power supply voltages for CMOS circuits which have an associated effect of lower threshold voltages to improve performance. Since the channel length for successive technology generations is reducing, threshold voltage and gate oxide thickness are also being scaled down to keep pace with the performance. Low threshold voltage results in exponential increase in leakage current because transistors cannot be switched off completely [1]. Power dissipates in the form of heat.

For a CMOS circuit, the total power dissipation includes dynamic and static components. The components of static power dissipation are sub threshold leakage, junction leakage, gate oxide leakage, gate induced drain leakage, punch through leakage [1], [2].

Techniques like LECTOR [3], GALEOR [4], Sleepy Keeper [5], Sleepy Pass Gate [6], Low Power State Retention Technique (LPSR) are used for leakage control. Each method has its own advantages and disadvantages. Some techniques use dual VT transistors; high VT transistors to reduce leakage and low VT transistors to improve speed of operation in critical sections of the circuit.

The proposed LPSR technique reduces leakage power and total power in combinational circuits and data path elements, which makes use of single VT transistors in all parts of the circuit to achieve low leakage power during sleep mode of operation and lower total power dissipation in Active mode. So comparing all the leakage control techniques this is the best technique to reduce total power dissipation.

2. Previous Techniques

LECTOR Technique

The LECTOR method inserts two extra Leakage Control Transistors (a P-type and an N-type) within the gate, in which the gate terminal of each Leakage Control Transistor is controlled by the source of the other. The effective stacking of transistors which increase the off resistance in the path from supply voltage to ground is the basic idea behind the LECTOR technique for the leakage power reduction. This is stated based on the observation from "a state is far less leaky with more than one OFF transistor in a path from supply voltage to ground compared to a state with only one OFF transistor in the path". The circuit diagram of a 2- input nand gate and block diagram using LECTOR technique is shown below.

GALEOR Technique

GALEOR technique reduces the leakage current flowing through the circuit for all possible input combinations by introducing stack effect. 2-input NAND gate using GALEOR technique is shown in the figure .In GALEOR technique, a leakage control high Vt NMOS transistor is placed between output and pull-up circuit and a leakage control, high Vt PMOS transistor is placed between output and pull- down circuitry.

This technique reduces the output voltage swing due to the threshold voltage loss caused by the high Vt MOS transistors, and in turn increases propagation delay through the circuit. The main disadvantage in using these techniques is there is no sleep mode which increases static leakage power dissipation in idle mode. In order to overcome these drawbacks sleepy keeper and sleepy pass transistor techniques are proposed.

SLEEPY KEEPER Approach

SLEEPY KEEPER uses a PMOS transistor in parallel to NMOS sleep transistor in the pull down path and NMOS transistor in parallel to PMOS sleep transistor in the pull up path. The extra retention transistors are connected to the output so that during sleep mode the logic state is maintained, but results in very high power dissipation.

Sleepy Pass Gate Approach

In Sleepy-Pass Gate approach two sleep transistors PMOS and NMOS are connected in parallel and inserted between Pull-Up and Pull-Down Networks of a CMOS logic gate to form a pass gate like structure. This has large power dissipation during pulsed operation.

Even though the above discussed techniques reduce the power dissipation this techniques cannot retain state during sleep operation. So in this paper a novel low power state retention technique is proposed where it retains the logical output state even in sleep mode.

3. Proposed Methodology

LPSR Technique

The LPSR technique uses a pair of NMOS and PMOS transistors above the pull up and below the pull down network of the CMOS circuit. General block diagram as well as schematics of LPSR NAND and NOR gates are as shown below. This technique has four modes of operation.

1. Active Mode: two sleep control signals namely slp = 0 and slpb = 1 are used to switch on the sleep transistors in leakage control block. Thus the virtual ground node VG is at ground potential and the virtual power node VP is at VDD.

2. Deep Sleep Mode: The sleep signals are held at slp = 1 and slpb = 0 states to switch off all the sleep transistors in both pull up and pull down leakage control blocks. Thus the actual power and ground path are disconnected virtually and the circuit experiences lower voltage across the nodes VP and VG.

3. State Retention Mode 1: The sleep signals are given as slp = 0 and slpb = 0. The circuit sees a voltage higher than ground at the node VG and full VDD at the node VP. The state retention takes place with low leakage current with the output at good logic 1 level.

4. State Retention Mode 0: The slp = 1 and slpb=1 are given as sleep control signals. The connection to actual ground is complete, the node VP is at lower VDD. Thus the state retention takes place with low leakage current with the output at good logic 0 level.

4. Simulation and Results

All the proposed techniques in this paper are designed for two input NAND gate and 2x1 multiplexer and simulated and functionally verified using 180nm CMOS technology files in Tanner EDA. Single VT transistors are used in all designs to show the performance benefits and comparison of different techniques. The logical functionality of gates is verified for all input combinations. Static power is calculated for all input combinations during active and sleep (idle) mode as well as dynamic power during clocked operations are all measured, and the delay analysis is done using EDA tools. The following figure shows the 2x1 Multiplexer circuit implemented using LPSR technique.

From the tables shown below we observe the dynamic power, static power for output logic-1 and logic-0 and the leakage power is less when compared LECTOR and GALEOR techniques. But slightly greater when compared to sleepy keeper approach and retains the state For LPSR technique the delay in active mode is less than all the approaches which increases the speed of the circuit. The following table shows the analysis for a 2x1 multiplexer.

5. Conclusion

LECTOR and GALEOR technique provide less dynamic power dissipation and more leakage power during active mode. But the main disadvantage is absence of sleep mode operation. The Sleepy Keeper approach maintains state during sleep mode at reduced level but results in large power dissipation during clocked operation because the output terminal is permanently connected to leakage control circuit and there is no deep sleep state. The Proposed LPSR technique has active mode static power on par with sleepy techniques and the least static power during deep sleep state and good state retention at low power. Thus the LPSR technique provides new methodology for the designers of low power VLSI circuits.

References

References

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