A Low-Voltage, Ultra-Low-Power, High-Gain Operational Amplifier Design for Portable Wearable Devices

Abstract

Based on the SMIC 0.13 um CMOS technology, this paper uses a 0.8 V supply voltage to design a low-voltage, ultra-low-power, high-gain, two-stage, fully differential operational amplifier. Through the simulation analysis, when the supply voltage is 0.8 V, the design circuit meets the ultra-low power consumption and also has the characteristic of high gain. The five-tube, fully differential, and common-source amplifier circuits provide the operational amplifier with high gain and large swing. Unlike the traditional common-mode feedback, this paper uses the output of the common-mode feedback as the bias voltage of the five-tube operational transconductance amplifier load, which reduces the design cost of the circuit; the structure involves self-cascoding composite MOS, which makes the common-mode feedback loop more sensitive. The frequency compensation circuit adopts Miller compensation technology with zero-pole separation, which increases the stability of the circuit. The input of the circuit uses the current mirror. A small reference current is chosen to reduce power consumption. A detailed performance simulation analysis of this operational amplifier circuit is carried out on the Cadence spectre platform. The open-loop gain of this operational amplifier is 74.1 dB, the phase margin is 61°, the output swing is 0.7 V, the common-mode rejection ratio is 109 dB, and the static power consumption is only 11.2 uW.

1. Introduction

In recent years, portable electronics and smart wearable devices (such as wireless bluetooth headsets, smart watches, digital cameras, and notebook computers) have become widely available. Under the background that it is difficult to increase the battery capacity in such devices, it is necessary to reduce the power consumption of the circuits in order to improve their endurance. Because of the power consumption and supply voltage’s positive exponential relationship, reducing the supply voltage has become one of the important initiatives to reduce the power consumption of portable products [1]. For analog circuits, operational amplifiers are the most important basic units and are widely used in various analog integrated circuits, such as digital-to-analog converters, low dropout linear regulators, and phase-locked loops. In addition, in some portable pressure sensor devices, the output signal of the mechanically sensitive element is generally very small, so it must be amplified and transformed by an amplifier processing circuit to meet the requirements of the application. The im plementation of low power consumption in analog circuits depends heavily on the power consumption of the operational amplifiers. The op-amp circuit presented in the reference [2] uses a 5.5 V supply voltage with great power consumption. The increase in power consumption can expose the product to the danger of high temperature operation and reduce the stability of the system’s operation. In order to comply with the development goals of low voltage and low power consumption, an op-amp is a better choice for today’s various portable electronic products and smart wearable devices. Based on the 0.13 um CMOS technology, this paper does not use the typical 1.2 V supply voltage, and adopts with a 0.8 V low supply voltage. A fully differential operational amplifier with low voltage, ultra-low power consumption, and high gain is designed.

2. Materials and Methods

The typical unipolar amplifiers have three structures: common source, common drain, and common gate [3]. In addition, based on the basic circuit, the amplifiers also have many commonly used structures, such as the telescopic cascode [4], the folded cascode [5], and the fully differential or two-stage op-amp structures.

The circuit of the sleeve-type cascode amplifier with a fully differential structure is shown in Figure 1a, and the gain expression is:

(1)$A_v=g_{m1}\left[\left(g_{m3}{r}_{o1}{r}_{o3}\right)//\left(g_{m5}{r}_{o5}{r}_{o7}\right)\right]$

The advantage of this structure is that it can provide high gain, but due to the large load, the output swing of the operational amplifier is greatly restricted. The output swing expression is:

(2)$V_{\mathit{out}}=2\left[VDD-\left(V_{OD1}+V_{OD3}+V_{OD0}+\left|V_{OD5}\right|+\left|V_{OD7}\right|\right)\right]$

In the formula, V_OD represents the overdrive voltage of each MOS tube. Another disadvantage of the telescopic cascode operational amplifier is that it will add extra poles, which will bring additional design costs.

The circuit of the fully differential structure of the folded cascode amplifier is shown in Figure 1b, and the gain expression is:

(3)$A_v=g_{m9}\left\{\left[\left(g_{m3}\left(r_{o1}//r_{o3}\right)r_{o9}\right)\right]//\left[\left(g_{m5}{r}_{o5}{r}_{o7}\right)\right]\right\}$

The output swing expression of this structure is:

(4)$V_{\mathit{out}}=2\left[VDD-\left(V_{OD1}+V_{OD3}+\left|V_{OD5}\right|+\left|V_{OD7}\right|\right)\right]$

Comparing Equations (2) and (4), it can be seen that the output swing of the folded cascode folded structure of the cascode operational amplifier has increased by 2 V_OD0 compared to the sleeve structure, but due to the equivalent outputs, the impedance of the folded cascode operational amplifier is smaller than that of the sleeve-type structure, so that the gain is significantly reduced. In addition, the folding structure has disadvantages, such as high power consumption, low pole frequency, and high noise generation.

Based on the analysis of the above theoretical structure, this paper adopts a two-stage operational amplifier circuit structure. The structure combines a fully differential five-tube operational transconductance amplifier (OTA) [6] and a common-source amplifier, which can meet high gain while also providing great swing. In addition, it has the advantages of simple bias circuit, a strong ability to suppress common-mode noise, and low power consumption.

The operational amplifier this paper designed is composed of an amplifying circuit module, a common mode feedback module, a frequency compensation module, and a current mirror bias module, as shown in Figure 2. The first stage of the amplifier circuit is a five-tube OTA circuit, and the second stage is a traditional common source amplifier circuit. The common-mode feedback module includes resistance common-mode detection and error amplification. This article uses a new common-mode feedback method that uses the signal after error amplification as the gate input of the five-tube OTA load, and the self-cascoding composite MOS structure is incorporated into the module. The frequency compensation module includes Miller capacitance compensation and zero resistance compensation. The overall design circuit of the op-amp is shown in Figure 3.

2.1. Amplifier Circuit Module

With the continuous development of integrated circuits, in some applications, the gain or output swing generated by the traditional unipolar operational amplifier cannot meet the requirements. For example, in [7], the gain of an operational amplifier with a unipolar folded cascode structure is 60.96 dB, and this structure has a low output swing. To solve this problem, this article designed a two-stage op-amp circuit to separate the gain and output swing. The first stage op-amp provides a higher gain for the circuit, and the second stage op-amp provides a great swing.

As shown in Figure 3, the first-stage operational amplifier circuit uses a fully differential five-tube OTA circuit, with N1 and N2 as the pair of input tubes; P1 and P2 as the equivalent current source output loads; and N7 in a saturated state, which acts as a tail current source. Then the first-stage operational amplifier voltage gain expression is:

(5)$A_{v1}=\frac{\partial V_{\mathit{out}1}}{\partial V_{in1}}=-g_{m1,2}\left(r_{n1,2}//r_{p1,2}\right)$

In the formula, g_m1,2 is the transconductance of N1 (or N2), r_n1,2 is the on-resistance of N1 (or N2), and r_p1,2 is the on-resistance of P1 (or P2).

The second stage operational amplifier circuit uses a typical common source amplifier circuit, with P5 and P6 tubes as the input tubes for the common source; and N5 and N6 tubes as the equivalent current source output load to increase the gain. Then the gain expression of the second stage op-amp is:

(6)$A_{v2}=\frac{\partial V_{\mathit{out}2}}{\partial V_{in2}}=-g_{m5,6}\left(r_{n5,6}//r_{p5,6}\right)$

In the formula, g_{m5, 6} is the transconductance of P5 (or P6), r_{n5, 6} is the on-resistance of N5 (or N6), and r_{p5, 6} is the on-resistance of P5 (or P6).

2.2. Common-Mode Feedback Module

When the op-amp uses a fully differential circuit structure, it is jammy to be unbalanced between the NMOS current source and the PMOS current source, which will cause an offset. The offset current flowing through the output resistance of the amplifier will produce a big voltage mismatch, forcing the side with the larger current enter the linear region. So, it is necessary to design a common-mode feedback (CMFB) circuit to allow each stage to achieve common-mode stability [8].

The common-mode feedback principle commonly used in two-stage op-amps is shown in Figure 4a. The principle is to use the result of the error amplifier to control the fully differential tail current source to achieve the common-mode feedback. The common-mode feedback module in this paper takes a new approach, as shown in Figure 4b. The output of both ends of the fully differential amplifier is passed through the common-mode detection circuit to obtain the common-mode voltage V_CM. The common-mode voltage V_CM is compared with the reference voltage V_COM. The compared error is amplified and output to the gates of P1 and P2 tubes to form a common-mode feedback loop. Ultimately, the output voltages Voutn and Voutp are equal to the reference voltage V_COM. This satisfies the feedback purpose and does not require an additional bias circuit to provide the bias voltage Vb1, reducing the design cost of the circuit. In addition, the error amplifier uses a self-cascoding composite structure to effectively increase the gain. This structure is suitable for low-voltage designs.

The self-cascoding composite MOS structure is shown in Figure 5.

In order for the self-cascoding composite structure to work properly, both M1 and M2 must be on, so the following conditions must be met:

(7)$\begin{array}{l}{V}_G-V_S-V_{TH}>0\\ V_G-V_X-V_{TH}>0\end{array}$

The above formula can be equated as follows:

(8)$V_X-V_S<V_G-V_S{=V}_{DSAT}$

Therefore M1 must be in the linear region with a small source-drain voltage. Thus, the equivalent V_DSAT of a self-cascoded MOS tube is close to the V_DSAT of a simple MOS tube. This makes the self-cascode structure suitable for applications in low voltage designs.

For the equivalent output resistance of this structure, the small signal model is shown in Figure 6.

The equivalent output resistance of a self-cascaded MOS tube is expressed as [9]:

(9)$r_{o\_eq}{=g}_{m2}{r}_2{r}_1-r_1-r_2\approx \left(g_{m2}{r}_1-1\right)r_2=\left({ng}_{m1}{r}_1-1\right)r_2$

The equivalent transconductance of the self-cascaded MOS tube is approximately equal to the transconductance of M1:

(10)$g_{m\_eq}=g_{m2}/m=g_{m1}$

From the above analysis, it is clear that the self-cascoded MOS tubes effectively increase the output resistance and improve the gain. The increase in gain makes the common-mode feedback loop more sensitive. Even if there is a small potential difference between the output voltage and the reference voltage V_COM, it can be amplified by the error amplifier to make the feedback loop work properly. Eventually, the output voltage is equal to the reference voltage.

2.3. Compensation Circuit Module

The output signal with phase shift is superimposed on the input signal, which will cause the op-amp to self-oscillate. The expression of the output function H(s) is:

(11)$H(s)=\frac{a_0+a_{1}s+a_2{s}^2+\dots +a_{m-1}{s}^{m-1}+a_m{s}^m}{b_0+b_{1}s+b_2{s}^2+\dots +b_{n-1}{s}^{n-1}+b_n{s}^n}=\frac{H_0\left(1+\frac{s}{z_1}\right)\left(1+\frac{s}{z_2}\right)\dots \left(1+\frac{s}{z_m}\right)}{\left(1+\frac{s}{p_1}\right)\left(1+\frac{s}{p_2}\right)\dots \left(1+\frac{s}{p_n}\right)}$

The amplitude-frequency and phase-frequency curves of the multi-pole op-amp system are shown in Figure 7.

The slope of the amplitude-frequency curve of the op-amp increases by −20 dB/dec with each passing pole, and the phase changes by 90°. Multiple poles cause changes in amplitude and phase frequency characteristics, which may make the system unstable and oscillate, causing its stability to be destroyed. This is where a frequency compensation circuit is needed to improve the stability of the system.

A typical two-stage op-amp with Mille compensation is shown in Figure 8. Node P is the main pole of the circuit. Assuming that the parasitic capacitance of junction P is C_P, the capacitance at junction P becomes C_P + (1 + A₂)C₁ after the addition of the Miller compensation capacitor. This causes the load capacitance of the main pole to increase; therefore the Miller compensation causes the main pole to move closer to the origin. The two-stage op-amp sub-primary pole analysis is shown in Figure 9.

When Miller compensation is not added, the frequency of the sub-major pole is:

(12)${\omega }_2=\frac{1}{R_L{C}_L}$

R_L is the load resistance, and C_L is the load capacitance. After adding Miller compensation, the frequency of the sub-major pole becomes:

(13)${\omega }_2{}^{,}=\frac{1}{\frac{1}{g_{m1}}{C}_L}=\frac{g_{m1}}{C_L}$

After adding Mille compensation, the frequency of the sub-major pole becomes larger. The sub-primary pole is shifted away from the origin. Finally, the analysis shows that the main poles of the op-amp are shifted to the left and the sub-major poles are shifted to the right after the Miller compensation. This increases the phase margin of the op-amp and improves the stability. This processing method is also called “pole splitting”.

In addition, the miller compensation capacitor will introduce a low frequency zero point [10]. This zero point contributes to a larger phase shift that shifts the phase intersection to the left, greatly reducing the stability of the op-amp. In this case, it is necessary to add a zeroing resistor in series with the Miller compensation capacitor to eliminate the effect of the zero point.

Based on the above theory, in this paper, the Mille capacitor and zeroing resistor are connected in series between the outputs of the first-stage op-amp and the second-stage op-amp to improve the stability of the circuit. Figure 10 shows the results of gain and phase without and with the addition of frequency compensation circuit. When the frequency compensation circuit is not added, the phase margin is 0.166°, as shown in Figure 10a, which is far from the conventional standard of 60° [11]. The circuit is extremely unstable. After adding the frequency compensation circuit, the phase margin is 61°, as shown in Figure 10b, and the circuit has good stability.

2.4. Current Mirror Bias Module

Both the fully differential module and the common-mode feedback module that have been determined above need to be set with the correct bias voltage to work normally. In order to achieve ultra-low power consumption of the op-amp and maintain the simplicity of the circuit, the bias circuits in this article are all current mirror bias [12] circuits, as shown in Figure 11.

In order to reduce the power consumption of the circuit as much as possible, the reference current source IREF is set to 2 uA in the cricuit, and the total operating current is 14 uA. According to the different currents required, this paper sets the appropriate width–length ratios of the N5, N6, N7, N8, and N9 tubes respectively, so that:

(14)${\left(W/L\right)}_5={\left(W/L\right)}_7={\left(W/L\right)}_6=2{\left(W/L\right)}_8=2{\left(W/L\right)}_9$

(15)$I_5=I_7=I_6=2I_2=2I_{REF}$

In the formula, (W/L) represents the width-to-length ratio of each MOS tube. Here, in order to reduce the influence of the channel length modulation effect on the current mirror, the module uses long-channel MOS tubes.

3. Results

The following reports the performance simulation of the op-amp circuit. Based on 0.13 um CMOS technology, the op-amp is simulated in the cadence spectre simulator. The simulation includes voltage gain, phase margin, transient analysis, common-mode rejection ratio (CMRR), noise analysis, and speed characteristic analysis. The simulated temperature is 27 °C, the supply voltage is 0.8 V, the corner is tt, and the static power consumption is only 11.2 uW. The layout of the op-amp is shown in Figure 12. The module design is symmetrical to reduce mismatch and DC offset and make the matching better. In addition, two protection rings are added to the periphery of the circuit to protect the internal circuit from external interference. To avoid the use of long metal interconnecting wires, contact holes are appropriately used as connecting wires.

3.1. Voltage Gain

This paper input a pair of ac small signals with opposite phases with a DC bias voltage of 0.6 V at the differential input terminals INN and INP. Then this paper performs a frequency scan on the operational amplifier. The frequency scan range is 10 Hz to 100 MHz. The result is shown in Figure 13. The low-frequency gain of the operational amplifier is 74.07 dB. After the frequency exceeded a certain range, the gain gradually decreased as the frequency increased.

3.2. Phase Margin

The phase margin is mainly used to describe the stability of the negative feedback system of an operational amplifier. Generally speaking, the phase margin of the operational amplifier needs to be no less than 45°. The greater the phase margin, the more stable the operational amplifier, but the speed will slow down. Therefore, considering it comprehensively, it is generally believed that a phase margin of 60° is the most suitable value [11]. If the phase margin is too large, it will slow down the speed characteristics of the op-amp. If the phase margin is too small, it will cause oscillation and stability problems. As shown in Figure 14, it can be seen the bandwidth corresponding to 0 dB in the gain simulation curve. This bandwidth is called the unity-gain bandwidth. It can be seen from the figure that the bandwidth is about 4.751 MHz. Then it can be seen the phase corresponding to the bandwidth in the phase simulation curve, the phase margin, which is about 61°.

3.3. Transient Analysis

This paper adds a pair of sinusoidal excitation sources with a DC voltage of 0.6 V, an AC component frequency of 1 KHz, and an amplitude of 200 uV to the differential input of the op-amp. Moreover, the two sinusoidal excitation sources have opposite phases. The simulation result is shown in Figure 15. The curves in the figure from top to bottom, respectively, represent the input terminals INP and INN; the output terminals OUTP and OUTN; and the final differential output. It can be seen that the unilateral output amplitude of the op-amp is 0.35 V, and the bilateral output amplitude is about 0.7 V. Compared with the supply voltage of 0.8 V, the operational amplifier designed in this article can provide a large output swing.

3.4. Common-Mode Rejection Ratio

Call the ratio of the differential-mode gain to the common-mode gain of the operational amplifier the common-mode rejection ratio, abbreviated as CMRR, and its expression is:

(16)$CMRR=\frac{A_D}{A_C}$

The CMRR reflects the ability of the op-amp to suppress common-mode interference [13]. It is generally believed that the higher the CMRR, the better the performance of the amplifier circuit. Carry on the differential mode gain simulation and the common-mode gain simulation to the operational amplifier. The results are shown in Figure 16. Know that the common-mode rejection ratio is stable within a certain low-frequency range from Figure 16. At 1 KHz, the common-mode rejection ratio is 109 dB. After the frequency increases to a certain value, its value decreases rapidly.

3.5. Noise Analysis

For the simulation of noise performance, the equivalent input noise is generally used to characterize the noise performance of the circuit. The equivalent input noise simulation of the two-stage operational amplifier is shown in Figure 17. The noise is mainly in the low-frequency band, which decreases as the frequency increases, and finally stabilizes. In addition, according to the noise simulation contribution report, the equivalent input noise can be reduced by increasing the length of the PMOS tube in the five-tube OTA circuit. This paper sets the length L of the PMOS tube to 4, 5, 6, 7, 8, or 9 μm, and the results are shown in Figure 17. However, the change in the length of the MOS tube inevitably leads to changes in the other performance metrics of the op-amp, and corresponding adjustments should be made according to requirements. Through a careful consideration of input noise and PMOS tube area, this paper chooses the PMOS tube with L = 5 um. When the frequency is 100 Hz, the equivalent input noise is $115\mathrm{nV}/\sqrt{\mathrm{Hz}}$.

3.6. Response Speed Analysis

The response speed is also one of the crucial indicators used to measure the quality of an op-amp. For the analysis of speed characteristics, two commonly used performance indicators are settling time and slew rate [14]. The setup time reflects how fast the op-amp processes the signal. The shorter the setup time, the faster the op-amp processes the signal. The slew rate reflects the ability of the output to follow the input. This paper inputs a big-step signal at the input end of the op-amp, and observes the voltage at the output end of the op-amp, as shown in Figure 18. The curves in the figure represent the response characteristics of the input terminals INN and INP; and output terminals OUTN and OUTP, respectively. Within the range of 1% stability accuracy, it can be obtained by calculation that the operational amplifier has the following results:

• Forward setup time: Time+ = 640 ns

• Negative setup time: Time− = 120 ns

• Forward slew rate: SR+ = (1.5450 V − 0.7773 V)/(0.64 us) = 1.19 V/us

• Negative slew rate: SR− = (1.5640 V − 0.8026 V)/(0.12 us) = 6.35 V/us

3.7. Influence of Temperature and Corner

In order to ensure the robustness of the design, the temperature and corner are simulated. The simulated operational amplifier gain and phase curves are shown in Figure 19 and Figure 20. The temperature range is from −100 to −100 °C, with 10 points in the middle. The corners are tt, ff, ss, fs and sf. In the figure, it can be seen that the temperature and corner have little effect on the gain and phase of the op-amp. The stability is unaffected, indicating that the operational amplifier is robust.

3.8. Power Consumption Analysis

The power consumption of the circuit can be obtained by measuring the current of the op-amp power supply pins. As shown in the Figure 21, a dc scan of the supply voltage is performed to obtain the static current and static power consumption of the op-amp. When Vdd = 0.8 V and Ivdd = 13.94 uA, the static power consumption of this op-amp is 11.2 uW. With the optimization of the circuit structure and the reduction of the supply voltage, the static power consumption of the op-amp is significantly reduced. However, this also sacrifices some other performance, such as gain and bandwidth.

4. Discussion

Table 1 compares the operational amplifier performance parameters of the design of this article and those of references. Compared with the design in [2], this article’s design has lower power consumption and a higher common-mode rejection ratio, but the gain and stability are weaker. For example, when the frequency is 1 KHz, the GBW of literature [2] is 10 MHz, and the GBW of this paper is 4.75 MHz. Then the gain difference is: 20 log(10/4.75) = 6.46 dB. For power consumption, the power consumption of literature [2] is 230 mW, and the power consumption of this paper is 0.0112 mW. Then the power consumption difference is: 10 log(230/0.0112) = 12.34 dB. It means that this paper only needs to gain 6.46 dB more and I will obtain 12.34 dB extra in my power consumption. My approach is better than that of literature [2]. Compared with the approaches in the literature [15,16], the paper has lower power consumption and higher gain, but the gain bandwidth and speed performance are weaker. For example, when the frequency is 1 KHz, the difference between the GBW of literature [16] and this paper is: 20 log(18.2/4.75) = 11.66 dB. The difference between the power consumption of literature [16] and that in this paper is: 10 log(13.86/0.0112) = 30.92 dB. It means that we only need to gain 11.66 dB more and I will obtain 30.92 dB extra in power my consumption. Again, the superiority of the method of this paper is proven. When compared to literature [17,18], the low voltage, low power consumption and high gain features of the design in this paper are also highlighted. In conclusion, the circuit designed in this paper has a definite advantage in terms of low power consumption by using a lower supply voltage. The static power consumption is only 3% of the power consumption of the literature [18] and 1‰ of the power consumption of the literature [16]. In addition, the meaning of the trade-off of consumption–response can be understood from the comparison. The “octagonal rule” of the analog design is satisfied.

5. Conclusions

Based on the 0.13 um CMOS technology, this paper designs a low-voltage (0.8 V), high-gain (74.1 dB), ultra-low power operational amplifier. This op-amp has great advantages in terms of low power consumption. The static power consumption is 11.2 uW, which is only 1‰ of the circuit power of the literature [16]. In addition, common-mode feedback and frequency compensation circuits are added to the circuit design to increase the stability of the operational amplifier circuit. Moreover, through the design of the size of the MOS tube, the gain of the circuit is increased. The influence of the channel length effect is reduced. The power consumption is reduced by using a small quiescent current. Through circuit simulation, the phase margin is 61°, the output swing is 0.7 V, the CMRR is 109 dB, the equivalent output noise is $115\mathrm{nV}/\sqrt{\mathrm{Hz}}$, and the slew rate is 6.35 V/us. By comparing this paper with the references, it is shown that the op-amp has good performance and excellent robustness. The low voltage and ultra-low power consumption make this op-amp have a broad application prospect in portable wearable devices.

Author Contributions

N.B. performed the experiments and analyzed the data; X.L. designed the method and wrote the paper; Y.X. provided suggestions for the paper. All authors have read and agreed to the published version of the manuscript.

Funding

This research is funded by the National Natural Science Foundation of China (No.61204039) and the Key Laboratory of Computational Intelligence and Signal Processing, Ministry of Education (No. 2020A012).

Institutional Review Board Statement

Not applicable.

Informed Consent Statement

Not applicable.

Data Availability Statement

All data included in this study are available upon request by contacting the corresponding author.

Conflicts of Interest

The authors declare that there is no conflict of interest regarding the publication of this paper.

Publisher’s Note: MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Figures and Table

Figure 1. Telescopic cascade and folding cascade.

Figure 2. Schematic diagram of the structure of the op-amp in this paper.

Figure 3. The overall operational amplifier circuit.

Figure 4. (a) The traditional common-mode feedback circuit. (b) The design of this article.

Figure 5. The self-cascoding composite MOS structure and equivalent simple MOS.

Figure 6. Small signal model of self-cascoding composite structure.

Figure 7. Amplitude-frequency curve and phase-frequency curve of a multi-pole system.

Figure 8. Classic two-stage op-amp Miller compensation.

Figure 9. Two-stage op-amp sub-major pole analysis.

Figure 10. The influence of frequency compensation circuit on the stability.

Figure 11. Current mirror bias circuit.

Figure 12. The op-amp layout.

Figure 13. Two-stage op-amp gain simulation.

Figure 14. The phase simulation.

Figure 15. Two-stage op-amp transient simulation.

Figure 16. Common-mode rejection ratio simulation.

Figure 17. The influence of PMOS length change on input noise.

Figure 18. Response speed simulation.

Figure 19. Temperature effect.

Figure 20. Corner effect.

Figure 21. Static current and static power consumption of the op-amp.

Table 1

The comparison of this op-amp with references.

Operational Amplifier Performance Parameters	Literature [2]	Literature [15]	Literature [16]	Literature [17]	Literature [18]	This Work
Number of stages	2	2	2	3	2	2
Echnology (um)	0.25	0.18	0.18	0.18	0.18	0.13
Vdd (V)	2.2; 5.5	3.3	1.8	1.5	1.8	0.8
Gain (dB)	120	72.21	71.275	70.8	63	74.1
Load Condition (pF)	N/A	N/A	10	30	1.0	3.0
Phase margin (°)	60	50.10	83	60.6	61.8	61
GBW (MHz)	10	10.05	18.2	2.12	0.14	4.75
CMRR (dB)	100	−30	60	N/A	88	109
SR+ (V/us)	6.0	45.45	2.48	1.6	29.7	1.27
SR− (V/us)	5.5	N/A	N/A	N/A	12.6	6.35
Power (mW)	230	0.192	13.86	0.084	0.30	0.0112

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