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Deep-UV (DUV) lithography has been developed to scale minimum feature sizes of devices on semiconductor chips to sub-halfmicron dimensions. This paper reviews early manufacturing experiences at the IBM Microelectronics Division with deep ultraviolet (DUV) lithography at a 248-nm wavelength. Critical steps in the processing of 1Mb DRAM, 16Mb DRAM, and logic gate conductors in devices are discussed. The evolution of DUV lithography tools is also briefly reviewed.
Introduction: Lithographic scaling
Lithographic scaling has historically been accomplished by optimizing the parameters in the Rayleigh model for image resolution: In this model, image resolution = k,A/NA, and depth of focus (DOF) = k2A/NA2, where A = exposure wavelength and NA = numerical aperture (kl, k2 = constants for a specific lithographic process). To pattern devices with decreasing feature sizes, photoresist exposure wavelengths were reduced and numerical apertures were increased.
During the last ten years, image resolution was sufficiently increased to scale minimum dimensions from 1-wm feature sizes for the 1Mb DRAM devices to 0.25-lm features for the 256Mb DRAM. The depth of focus is proportional to the inverse of the square of the numerical aperture; thus, if resolution is enhanced by increasing NA, the depth of focus becomes very small. If the resolution is enhanced by decreasing the wavelength, the corresponding decrease in depth of focus is less severe. As shown in Figure 1, for lithography at the diffraction limit, a shorter wavelength provides more depth of focus at a particular resolution value because the shorter wavelength allows a lower-NA photolithography tool to achieve equivalent resolution.
The IBM Microelectronics Division has been active in the evolution of lithography throughout the development of the semiconductor industry (Figure 2). DRAM production of 64Kb devices utilized scanning exposure equipment operating at a G-line wavelength of 436 nm. These tools were capable of operating at several different exposure wavelengths, including 436 nm, 313 nm, and 245 nm [1]. IBM used these tools for 256Kb DRAM chips by formulating a resist, TNS, which was functional at the 313-nm exposure region [2], allowing the critical feature size to be scaled from 2 ,um to 1.4 /am. This approach was repeated for 1Mb DRAM chips, and a 245-nm exposure region was used to obtain the 1-/am critical features with the same tool set, which...