A Novel Radiation-Hardened CCDM-TSPC Compared with Seven Well-Known RHBD Flip-Flops in 180 nm CMOS Process

Abstract

Numerous radiation-hardened-by-design (RHBD) flip-flops have been developed to increase the dependability of digital chips for space applications over the past two decades. In this paper, the radiation immunity and performance of seven well-known RHBD flip-flops are discussed. A novel cross-connected dual modular redundant true single-phase clock (TSPC) D flip-flop (CCDM-TSPC) is proposed. The presented CCDM-TSPC replaces the typical master-slave D flip-flop (MS-DFF) with the fundamental TSPC structure to shorten the circuit’s propagation time. All sensitive points in the circuit are radiation-hardened by using means of cross-connection. The simulation results of the SPECTRE tool show that CCDM-TSPC is completely immune to single-event upsets (SEUs). CCDM-TSPC reduces the C-Q delay by 75% and the layout area by 85% compared with the traditional triple modular redundancy D flip-flop (TMR-DFF).

1. Introduction

The continuous reduction of feature size and the decrease of node parasitic capacitance increase the probability of single-event transients (SETs) on chips due to spatial radiation [1,2]. SETs are caused by high-energy particles in the universe that can ionize extra electron-hole pairs as they penetrate through the silicon substrate [3]. These electron-hole pairs are collected by the sensitive node of the circuit, resulting in an instantaneous change in the voltage of the sensitive node. Single-event upsets (SEUs) may be caused when the amplitude of the transient signal is too large or the duration is too long [4,5]. Unlike an SET, which only generates a voltage glitch at the sensitive node, an SEU is a soft error that reverses the latch and locks it until the next circuit refresh. Although the SEU will not cause catastrophic damage to the system, it may also cause system failure. Therefore, advanced microprocessors must take relevant protection measures to avoid SEUs [6,7,8].

Since the packaging material itself emits alpha particles, the packaging is not considered radiation-hardened. Common techniques to improve SEU robustness include, but are not limited to:

• Layout level: An example of layout level is using offset circuits that create voltage changes opposite the sensitive nodes in accordance with the charge-sharing principle as a means of eliminating SETs [9,10].

• System level: For instance, error correction codes in the memory structure can automatically fix the code of mistakes brought on by SEUs [11,12,13]. However, this method is ineffective for sequential logic circuits dispersed throughout the chip.

• Circuit level: Radiation-hardened-by-design (RHBD) technology is the circuit-level approach. Because it may enhance the radiation immunity of chips and offer significant design freedom without depending on external conditions, RHBD technology is frequently used in the high-reliability design of circuits [14,15,16,17].

The RHBD technology for D flip-flops can be summarized into two main categories. One is to improve the SEU robustness of the latch structures in D flip-flops. The circuit diagram of the master-slave D flip-flop (MS-DFF) is shown in Figure 1. MS-DFF has two back-to-back inverter structures that do not have radiation immunity. Figure 2a depicts the structure of a dual interlocked storage cell (DICE), which contains four storage nodes [18,19,20,21]. DICE has strong SEU robustness since the surrounding undisturbed nodes will correct the affected node when an SET occurs in one of the nodes. If the latches in a D flip-flop are replaced by DICE structures, then the D flip-flop will naturally be radiation-hardened. Another innovative Quatro latch with strong SEU robustness and application to D flip-flops is shown in Figure 2b [22,23,24,25].

Redundancy is another RHBD technology type for D flip-flops. Triple modular redundancy (TMR) [26], which has strong SEU robustness, is one of the most well-known redundancy topologies. The TMR structure triples the circuit, and a voter votes among the three outcomes to determine the final logic value. The drawback of TMR is that the chip area and power consumption have tripled. Another redundant structure that is largely recommended by designers is dual modular redundancy (DMR) [27]. The DMR copies the basic D flip-flop in duplicate and outputs the result through a C-element, consuming only twice as much power as the original circuit. It is worth proposing that the redundancy method is also applicable to the other two basic structures of D flip-flops, that is, the true single-phase clock (TSPC) structure shown in Figure 3a and the clocked CMOS (C²MOS) structure shown in Figure 3b [28,29]. These two structures are improved compared with the conventional master-slave D flip-flop (MS-DFF). The TSPC D flip-flop (TSPC-DFF) only operates with a single-phase clock and, thus, reduces the load on the clock. The C²MOS D flip-flop (C²MOS-DFF) is immune to clock overlap.

The contributions of this paper are the following:

• A relatively thorough review and classification of existing D flip-flops for radiation immunity is produced, so as to better support future radiation immunity research in sequential logic circuits.

• A novel cross-connected dual modular redundant TSPC D flip-flop (CCDM-TSPC) is proposed. Because every vulnerable area of the circuit is shielded by using means of cross-connection, CCDM-TSPC is totally immune to SEUs.

• The C-Q delay, power consumption, and power delay product (PDP) of CCDM-TSPC are the smallest compared with seven mentioned traditional structures. In comparison with the conventional TMR and DMR structure, the layout area of CCDM-TSPC has been decreased by more than 75%.

The remainder of this paper is organized as follows: In Section 2, the radiation immunity strategies of D flip-flops are further outlined. Seven typical structures are investigated for SEU robustness. In Section 3, a novel CCDM-TSPC structure is proposed, and its operation and soft error robustness are analyzed in detail. Section 4 displays the performance evaluation of CCDM-TSPC and seven existing structures in terms of design complexity, C-Q delay, power consumption, PDP, layout area, and SEU robustness. Finally, this paper is concluded in Section 5.

2. Existing Soft Error Robust Flip-Flop Designs

The arrangement and combination of several radiation-hardened D flip-flop structures are possible using the three widely used D flip-flop structures, MS-DFF, TSPC-DFF, and C²MOS-DFF, as well as the two radiation-hardened latch structures, DICE and Quatro. The circuits of seven typical existing structures are created in this section using the same 180 nm CMOS technology. A double exponential current source is employed to mimic SETs [30]. The circuits are simulated with the SPECTRE tool at a 5 V supply voltage and a 100 MHz clock. All of the transistors have a W/L of 2/0.5 unless otherwise stated.

2.1. DICE-DICE

D flip-flops consisting of two cascaded DICE latches (DICE-DICE) belong to a class of those that improve SEU robustness by changing the latch structure [31]. The circuit diagram of DICE-DICE is shown in Figure 4. The input signal directly drives two nonadjacent nodes, X and X1, in the first DICE. The other two nonadjacent nodes of the first DICE drive the two nonadjacent nodes of the second DICE. The output stage contains a C-element, which is controlled by the other two nonadjacent nodes of the second DICE. DICE-DICE has strong SEU robustness due to the radiation immunity of each latch.

The normal operation of DICE-DICE is shown in Figure 5a, where the output signal is correct. The simulation results for SETs occurring at nodes X2, Z2, and Z3 are shown in Figure 5b. It appears that SEUs have no effect on DICE-DICE. Although DICE-DICE has no redundancy in the overall circuit, each DICE has a larger layout area than a typical latch. The transmission delay of DICE is relatively large due to the fact that only two storage nodes are operated during read and write. Of course, the transmission delay will be improved if the four storage points are read and written at the same time without considering the power consumption. Despite this, DICE-DICE is not overlooked by designers due to its excellent radiation immunity.

2.2. TMR-DFF

The circuit diagram of the TMR D flip-flop (TMR-DFF) is shown in Figure 6 [32]. TMR-DFF replicates the identical flip-flop structure and outputs the final result using the voter. Each discrete D flip-flop is a fundamental MS-DFF structure, as shown in Figure 1. For the sake of circuit simplicity, each MS-DFF is represented by a symbol. When an SEU occurs in any flip-flop due to particle attack on sensitive nodes in the circuit, the remaining two unaffected flip-flops will keep the correct output result, and the output of the voter will not be affected. Thus, TMR-DFF is completely immune to SEUs.

Figure 7a shows the TMR-DFF waveform during normal operation, and Figure 7b shows the simulation result when sensitive nodes of TMR-DFF receive particle attack. It is evident that TMR-DFF is immune to simulated particle attacks against node Z, node Z1, and node Z2. It can be inferred that TMR-DFF can still maintain the correct output when particles attack each trigger. TMR-DFF is one of the most dependable options in radiation-hardened design, but this structure is unsuitable for low power consumption occasions because of three times the circuit area.

2.3. DM-DFF

Figure 8 depicts the circuit design for the dual modular redundancy D flip-flop (DM-DFF) [33]. The DM-DFF circuit consists of two stages. Two identical MS-DFFs make up the first stage, whereas a C-element is present in the second-stage. This structure has two redundant signals, Z and Z1, which are coupled by the C-element and increase its radiation immunity. The output of the C-element will maintain the original signal even if the output of one MS-DFF flips owing to a particle impact, while the output of the other MS-DFF remains unaffected.

Figure 9a depicts DM-DFF in regular operation, with the output signal being accurate. Figure 9b depicts the behavior of the simulated SETs at nodes X, Y, and Z in the circuit. It is obvious that DM-DFF is completely immune to radiation. However, in addition to the circuit area and power consumption being twice that of traditional MS-DFF, there are still two issues that need to be resolved. One is that the reading and writing of latches during the sampling phase or the holding phase lengthens the system’s latency. Another issue is that the soft error issue brought on by clock overlap becomes worse when multiple-phase clocks are employed.

2.4. DM-TSPC

TSPC-DFF can also be radiation-hardened with redundant methods. The circuit diagram of the dual modular TSPC D flip-flop (DM-TSPC) is shown in Figure 10 [34]. The input stage of DM-TSPC consists of two identical TSPC-DFFs, while the output stage contains a C-element. In this way, SETs generated at node X, node Y, and node Z within the TSPC structure will not cause SEUs in the output stage.

In fact, TSPC-DFF has two C-elements, the first of which is a clock-controlled C-element and the second of which is a standard C-element. However, one of the input signals of the regular C-element is signal Z, which is not redundant, and the other input signal Z1 is generated by signal Z passing through the NMOS controlled by the clock. It can be inferred that an SET occurring at node Z will be transmitted to node Z1 through the NMOS and affect the final output result. Figure 11a is the normal working waveform of DM-TSPC, and Figure 11b is the simulation result of SETs’ behavior occurring at sensitive nodes, which confirms the previous inference.

2.5. TSPC-Quatro

The output stage of DM-TSPC can not only use a C-element but also use a Quatro structure to latch the output signal. As shown in Figure 12, TSPC-Quatro is a new radiation-hardened structure composed of DM-TSPC and Quatro latch [35]. The Quatro structure latches the output signal Z and its inverse signal Z1. The output of the entire trigger is obtained from node Z through an inverter. It is important to point out that TSPC-Quatro is not truly immune to radiation.

Figure 13a is the normal working waveform of TSPC-Quatro. Figure 13b is the waveform when sensitive nodes of TSPC-Quatro are attacked by simulated particles. There are two reasons for the insufficient radiation immunity of TSPC-Quatro. First, the soft error at node Z can be transmitted to the output quickly so that voltage transients can be observed at the output node. Second, the Quatro latch is not entirely immune to radiation. For instance, it is assumed that node Z stores logic 0, and when it is attacked by particles, it abruptly switches to logic 1. At this time, transistor M6 and transistor M8 turn on. Node Z3 and node Z1 suddenly flip to logic 0, and then transistor M1 switches on, and node Z2 is mutated to logic 1. As a consequence, the entire Quatro latch is flipped and an SEU occurs.

2.6. C²MOS-Quatro

Another radiation-hardened D flip-flop (C²MOS-Quatro) is created if the TSPC-DFF in the TSPC-Quatro structure is modified to C²MOS-DFF [36]. A C²MOS-Quatro circuit diagram is shown in Figure 14. There are two identical C²MOS-DFFs in the first stage. The output signal produced by the previous stage is latched in the second-stage using a Quatro structure. The output of the first C²MOS-DFF serves as the output of the entire circuit.

Figure 15a is the normal working waveform of C²MOS-Quatro, and Figure 15b is the simulated waveform when sensitive nodes of C²MOS-Quatro are attacked by particles. It can be seen that C²MOS-Quatro is not completely immune to radiation. The reason is that C²MOS-Quatro and TSPC-Quatro have the same issue. The final output node of the circuit will still receive the soft error even though it is promptly fixed at node Q. The Quatro structure itself does not have robust-enough radiation protection. Fortunately, C²MOS-Quatro has the advantages of low transmission delay and a small layout area.

2.7. TSPC-DICE

Another radiation-hardened D flip-flop (TSPC-DICE) can be created by combining a single TSPC-DFF with a DICE latch [37]. Figure 16 depicts a TSPC-DICE circuit diagram. TSPC-DICE consists of two-stage circuits. One TSPC-DFF serves as the input stage. A C-element makes up the output stage. The output signal of TSPC-DFF serves as an input signal of the C-element, while the output signal of the TSPC-DFF generates another input signal of the C-element through a clock-controlled NMOS. These two signals are latched by the DICE structure.

TSPC-DICE has the same problem as DM-TSPC since the input signals of a C-element are generated in the same way. The transient voltage at node Z will become propagated to node Z1 through the low impedance path of the NMOS and affect the final output. The input stage of TSPC-DICE also does not take any protective measures, so the simulated high-energy particle bombardment at node X and node Y may produce SEUs. Figure 17a shows the normal operation waveform of TSPC-DICE. Figure 17b shows the waveform when sensitive nodes of TSPC-DICE receive a simulated particle attack. The results confirm the above analysis.

3. Proposed Soft Error Robust Flip-Flop Designs

In this section, a novel cross-connected dual modular redundant TSPC D flip-flop (CCDM-TSPC) is presented. The working process and SEU robustness of CCDM-TSPC are described and analyzed in detail. The simulation results of the SPECTRE tool show that CCDM-TSPC has strong SEU robustness.

3.1. Working

The circuit diagram of CCDM-TSPC is shown in Figure 18. The input stage contains a basic TSPC-DFF and a redundant TSPC-DFF, while the output stage contains a C-element. Nodes X, X1, Y, Y1, Z, and Z1 are cross-connected at the outputs of the first-stage inverter, the second-stage inverter, and the third stage inverter, respectively. When the clock is at a low level, the input stage inverters sample the inverted D input on nodes X and X1. The second-stage inverters are in the precharge mode, with M4 and M14 charging up nodes Y and Y1 to the power supply voltage. The third stage inverters are in the hold mode, since M8, M9, M18, and M19 are off. During the low phase of the clock, the input to the final inverters holds its previous value. Therefore, nodes Z and Z1 and output Q are stable. On the rising edge of the clock, the second-stage inverters evaluate. If X and X1 are high on the rising edge, nodes Y and Y1 discharge. The third-stage inverters are on during the high phase, and the low level on nodes Y and Y1 is passed to output Q. If X and X1 are low on the rising edge, nodes Y and Y1 stay in charge mode. The third-stage inverters are also on during the high phase, and the high level on nodes Y and Y1 is passed to output Q. This is the working mode of CCDM-TSPC.

3.2. Soft Error Analysis

The excellent radiation immunity of CCDM-TSPC results from the cross-connection between the basic TSPC-DFF and the redundant TSPC-DFF. The circuit of CCDM-TSPC contains six sensitive nodes, which are nodes X, X1, Y, Y1, Z, and node Z1. The discharge path at node Y contains three transistors, M5, M6, and M7. When the clock is at a low level, node Y is in the precharge state. When the clock is at a high level, M7 is on. The discharge at node Y depends not only on the state of node X but also on the state of node X1. When node X is at a low level, node X1 is also at a low level. At this time, the mutation of any point to a high level cannot cause node Y to discharge. When node X is at a high level, node X1 is also at a high level. At this time, the discharge speed of node Y is extremely fast, and the level of node Y is rapidly pulled down. Thus, as long as the level of nodes X and X1 does not jump from high to low on the edge of the clock, the state of node Y does not have an error.

The SEU robustness of node Z and output Q is analyzed below. The third-stage inverter of CCDM-TSPC is a clock-controlled CMOS inverter. The driving signals of the gates of PMOS and NMOS come from the precharge points of the basic TSPC-DFF and the redundant TSPC-DFF, respectively. Assume that nodes Y and Y1 are at a high level and nodes Z and Z1 are at a low level. When node Y mutates to a low level, M18 and M20 are in high-resistance states, and the state of node Z1 keeps the low level unchanged. M8 is in a transient conduction state, while M10 is in a continuous conduction state, the node Z will have a transient voltage fluctuation and then return to a low level. Assume that nodes Y and Y1 are at a low level and nodes Z and Z1 are at a high level. When node Y mutates to a high level, M8 and M10 are in a high-resistance state, and the state of node Z keeps the high level unchanged. M20 is in a transient conduction state, while M18 is in a continuous conduction state, so node Z will recover to a high level after a transient voltage fluctuation. The output stage of CCDM-TSPC consists of a C-element, so the state of output Q will not be affected by a single voltage change at either node Z or Z1.

Due to the symmetry of CCDM-TSPC, the analysis of nodes X, Y, and Z also applies to nodes X1, Y1, and Z1. Figure 19a shows the normal working waveform of CCDM-TSPC. Figure 19b shows the waveforms of sensitive nodes under a simulated particle attack. The results confirm the above analysis.

4. Performance Evaluation and Analysis

In this section, the performance of CCDM-TSPC and the other seven comparison structures is evaluated in six aspects. There are design complexity, C-Q delay, power consumption, power delay product (PDP), layout area, and SEU robustness. Design complexity is the number of transistors used to design a circuit. The C-Q delay represents the delay from the rising edge of the clock to the steady state of the trigger output. Power consumption is the product of the average voltage and the average current of the power supply. PDP is the product of the time taken to complete a computational task and the average power consumption [38]. Here, it refers to the energy required for the trigger to complete a state flip. The layout area is the total area of all transistors and layout wiring. All data were simulated using the SPECTRE tool. Table 1 shows the data for five indicators for the eight structures. The performance of the eight structures is shown on a radar chart in Figure 20. It can be seen intuitively that CCDM-TSPC has better performance on the basis of satisfying complete immunity to SEUs. In addition, the impact of process variation on the proposed CCDM-TSPC is evaluated by Monte Carlo simulations in Section 4.7.

4.1. Design Complexity

The flip-flops with the largest number of transistors are TMR-DFF and DM-DFF, which require 78 and 46 transistors, respectively. CCDM-TSPC requires 24 transistors, which is about the same as DM-TSPC and TSPC-DICE. DICE-DICE contains 36 transistors, while TSPC-Quatro and C²MOS-Quatro require 25 and 30 transistors, respectively.

4.2. C-Q Delay

It takes longer to change the state of a DICE or Quatro latch than to drive a regular latch. DICE-DICE with two DICE structures has the longest C-Q delay of 0.86 ns, while TMR-DFF and DM-DFF both have a C-Q delay of 0.5 ns. The C-Q delay of CCDM-TSPC is only 0.13 ns, which is the smallest among the eight structures. The C-Q delay of CCDM-TSPC is reduced by 85% compared with DICE-DICE and 75% compared with TMR-DFF and DM-DFF. The delay of the other structures is about 0.3 ns.

4.3. Power Consumption

There is a positive correlation between the power consumption and the design complexity of flip-flops. The power consumptions of DM-TSPC and TSPC-DICE with few transistors are only 2.62 and 2.65 mW, respectively. DICE-DICE has a power consumption of 3.72 mW, which is the largest of all the structures. In addition, both DM-DFF and C²MOS-Quatro need roughly 2.7 mW of power. The power consumption of TMR-DFF and TSPC-Quatro is similar, at about 3 mW. Among all the structures, the proposed CCDM-TSPC has the lowest power usage at 2.61 mW.

4.4. Power Delay Product (PDP)

The PDP of CCDM-TSPC is 8.47 pJ, which is ranked as the smallest among all the mentioned structures together with DM-TSPC. Due to the large amount of energy required to drive a DICE latch, DICE-DICE has the highest PDP of 15.51 pJ among all structures. The PDP of TMR-DFF with a larger number of transistors is also relatively large. CCDM-TSPC shows 45% lower PDP when compared with DICE-DICE and 28% lower PDP when compared with TMR-DFF.

4.5. Layout Area

The layout design of all the mentioned structures is shown in Figure 21. The area of the layout depends heavily on the number of transistors. The TMR-DFF with 78 transistors has the largest layout area of 2880 μm². TSPC-DICE has the smallest layout area of 319 μm² because it does not contain any redundant structure. The layout area of DICE-DICE and DM-DFF is over 1000 μm². The layout area of the proposed CCDM-TSPC is 456 μm². Compared with TMR-DFF, DM-DFF, and DICE-DICE, the layout area of CCDM-TSPC is reduced by 85%, 75%, and 60%, respectively.

4.6. SEU Robustness

The SEU robustness of the eight flip-flops can be summarized from the simulation waveforms in Section 2 and Section 3. The SEU robustness of TSPC-DICE is poor. DM-TSPC, TSPC-Quatro, and C²MOS-Quatro are not truly radiation-hardened. CCDM-TSPC, TMR-DFF, DM-DFF, and DICE-DICE are completely immune to SEUs. However, compared with TMR-DFF, DM-DFF, and DICE-DICE, CCDM-TSPC has great advantages in power consumption, layout area, and C-Q delay.

4.7. Process Variation

Monte Carlo simulations are used in this section to evaluate the effect of process variation on the proposed CCDM-TSPC. In order to increase the reliability of the simulation results, the number of sampling points in Monte Carlo simulations is set to 5000. Figure 22 depicts the Monte Carlo analysis results of C-Q Delay, power, and PDP on process variation. C-Q delay has a mean value of 128.283 ps, which is close to the previous simulation result of 0.13 ns. The standard deviation of C-Q delay is 1.55846 ps, which is less than 1.3% of the mean. The mean value of power is 2.61512 mW, which is equal to the aforementioned simulation result of 2.61 mW. The standard deviation of power is 25.1057 μW, which is only 0.96% of the mean. PDP has a mean value of 8.45494 pJ, which is close to the simulation result of 8.47 pJ. The standard deviation of PDP is 97.6632 fJ, which is less than 1.2% of the mean. The results of Monte Carlo simulations indicate that the C-Q delay, power, and PDP of the proposed CCDM-TSPC are robust against process variation.

5. Conclusions

The CCDM-TSPC proposed in this paper can strengthen the radiation immunity of all sensitive points by using cross-connection. The techniques of radiation immunity of triggers in the past are systematically compiled and categorized in this paper. The most common RHBD technology for radiation-hardened triggers is to reinforce the latch structures or design redundant circuits. CCDM-TSPC, along with seven other typical flip-flop circuits, are implemented at the same 180 nm node. According to the simulation results of the SPECTRE tool, CCDM-TSPC is totally immune to SEUs. The PDP of CCDM-TSPC is the smallest among all the structures mentioned. When compared with DICE-DICE, the C-Q delay of CCDM-TSPC is 85% shorter. The layout area of CCDM-TSPC has been reduced by more than 75% when compared with the conventional redundancy structures TMR-DFF and DMR-DFF. The results of Monte Carlo simulations demonstrate that the performance of the proposed CCDM-TSPC is robust against process variation.

Author Contributions

Conceptualization, S.W. and L.W.; methodology, S.W.; software, M.G.; data curation, Y.L.; writing—original draft preparation, S.W.; writing—review and editing, Y.W. All authors have read and agreed to the published version of the manuscript.

Acknowledgments

The authors would like to thank Lixin Wang of the Institute of Microelectronics of the Chinese Academy of Sciences (IMECAS) for his guidance and suggestions on the circuit structure of this paper.

Conflicts of Interest

The authors declare no conflict of interest.

Publisher’s Note: MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Figures and Table

Figure 1. Schematic diagram of MS-DFF.

Figure 2. Schematic diagram of two common latches: (a) DICE; (b) Quatro.

Figure 3. Schematic diagram of two common D flip-flops: (a) TSPC-DFF; (b) C2MOS-DFF.

Figure 4. Schematic diagram of DICE-DICE.

Figure 5. DICE-DICE: (a) simulation waveform of DICE-DICE without SETs; (b) simulation waveform of DICE-DICE with SETs.

Figure 6. Schematic diagram of TMR-DFF.

Figure 7. TMR-DFF: (a) simulation waveform of TMR-DFF without SETs; (b) simulation waveform of TMR-DFF with SETs.

Figure 8. Schematic diagram of DM-DFF.

Figure 9. DM-DFF: (a) simulation waveform of DM-DFF without SETs; (b) simulation waveform of DM-DFF with SETs.

Figure 10. Schematic diagram of DM-TSPC.

Figure 11. DM-TSPC: (a) simulation waveform of DM-TSPC without SETs; (b) simulation waveform of DM-TSPC with SETs.

Figure 12. Schematic diagram of TSPC-Quatro.

Figure 13. TSPC-Quatro: (a) simulation waveform of TSPC-Quatro without SETs; (b) simulation waveform of TSPC-Quatro with SETs.

Figure 14. Schematic diagram of C2MOS-Quatro.

Figure 15. C2MOS-Quatro: (a) simulation waveform of C2MOS-Quatro without SETs; (b) simulation waveform of C2MOS-Quatro with SETs.

Figure 16. Schematic diagram of TSPC-DICE.

Figure 17. TSPC-DICE: (a) simulation waveform of TSPC-DICE without SETs; (b) simulation waveform of TSPC-DICE with SETs.

Figure 18. Schematic diagram of CCDM-TSPC.

Figure 19. CCDM-TSPC: (a) simulation waveform of CCDM-TSPC without SETs; (b) simulation waveform of CCDM-TSPC with SETs.

Figure 20. Radar chart of the performance of the mentioned radiation-hardened structures.

Figure 21. Layout design of the mentioned radiation-hardened structures.

Figure 22. Monte Carlo simulation results of process variation: (a) C-Q delay, (b) power, and (c) PDP.

Table 1

Performance summary and comparison for radiation-hardened D flip-flops.

	Number ofTransistors	C-Q Delay(ns)	Power(mW)	PDP(pJ)	Layout Area(μm2)	Single-PhaseClock *	SEURobustness
DICE-DICE [31]	36	0.86	3.72	15.51	1144	×	OK
TMR-DFF [32]	78	0.50	3.08	11.77	2880	×	OK
DM-DFF [33]	46	0.50	2.72	10.14	1850	×	OK
DM-TSPC [34]	22	0.21	2.62	8.47	390	√	No
TSPC-Quatro [35]	25	0.29	3.18	10.93	598	√	No
C2MOS-Quatro [36]	30	0.34	2.70	10.76	754	×	No
TSPC-DICE [37]	22	0.23	2.65	9.36	319	√	Poor
CCDM-TSPC	24	0.13	2.61	8.47	456	√	OK

* A structure that does not use a true single-phase clock requires two additional inverters to obtain the clock and the complementary clock, which are omitted from the corresponding figure.

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