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Journal of ELECTRONIC MATERIALS, Vol. 43, No. 11, 2014
DOI: 10.1007/s11664-014-3332-x
2014 The Minerals, Metals & Materials Society
An RDL UBM Structural Design for Solving Ultralow-K Delamination Problem of Cu Pillar Bump Flip Chip BGA Packaging
K.M. CHEN,1,2,5 C.Y. WU,1 C.H. WANG,1 H.C. CHENG,3,6 and N.C. HUANG4
1.United Microelectronics Corporation, No. 3, Li-Hsin Rd. II, Hsinchu Science Park, Hsinchu 300, Taiwan, ROC. 2.Department of Mechanical Engineering, National United University, Miaoli, Taiwan, ROC. 3.Department of Aerospace and Systems Engineering, Feng Chia University, No. 100, Wenhwa Rd., Seatwen, Taichung 40724, Taiwan, ROC. 4.Siliconware Precision Industries Corporation, Taichung, Taiwan, ROC. 5.e-mail: [email protected]. 6.e-mail: [email protected]
Copper (Cu) pillar bumps tend to induce high thermalmechanical stress during environmental tests and fabrication processes due to the high hardness of Cu, especially when applied with an ultralow-K (ULK) chip. A previous experiment showed that interfacial delamination was often observed in the ULK layers of conventional Cu pillar bump-type ip chip ball grid array (FCBGA) packages under thermal cycling, where under bump metallurgy (UBM) layers directly sit on the metal pads of silicon chips (herein termed direct UBM structure). In this study, a UBM pad relocation scheme through redistribution layer (RDL) technology (herein termed RDL UBM structure) is proposed to relieve the stress or ULK delamination issue. The proposed technique is tested on Cu pillar bump-type FCBGA packages subjected to thermal loading, the effectiveness of which is demonstrated through nite element stress simulation and experimental reliability tests. Simulation results reveal that the RDL UBM structure can greatly reduce the maximum stress in the ULK layers by as much as about 10% to 44%. Besides, it turns out that the Cu pillar bump-type FCBGA packages with the RDL UBM structure show good interconnect reliability performance in terms of thermal cycling, highly accelerated stress, and high-temperature storage.
Key words: Cu pillar bump, under bump metallurgy, ultralow-K, delamination, nite element analysis, reliability test
INTRODUCTION
As the line width and spacing of advanced semiconductor devices become smaller, ip chip (FC) technology must handle the increase in input/output (I/O) interconnect density. However, FC technology with solder bumps will soon approach its technical limit because solder bumps possess a larger diameter. By contrast, copper (Cu) pillar bump-type FC packaging provides a more promising and enabling solution as bump...