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Introduction
Recently, flexible circuits have attracted a lot of attention because of their conformal properties, which create possibilities for many applications in portable electronics, sensor array systems and aerospace, etc. ([2] Balde, 2003; [7] Burghartz, 2010). The flexibility of an end product is often limited by the rigid components mounted on the surface of the substrate. The introduction of ultra-thin chips, which are more flexible, in contrast to bulk silicon chips, can further enhance the mechanical flexibility of the electronic circuitry.
A thinned silicon die can be either flip bonded onto or embedded into thin film substrates ([3] Banda et al. , 2008; [6] Boettcher et al. , 2008; [9] Chen et al. , 2000). The chip embedding approach is a promising candidate for the next generation System-in-Package (SiP) technology by reason of its high-density interconnection capability and excellent electrical performance ([4] Boettcher et al. , 2010). One of the most prominent embedding approaches is Chip-in-Polymer (CiP) technology developed by Fraunhofer IZM in corporation with TU Berlin. The basic concept of CiP is to laminate thinned die in dielectric resin, followed by making contact to the chip bond pads by laser ablation and direct metallization ([5] Boettcher et al. , 2007). IMEC presented a similar technology, UTCP, in which a thinned die (typically 20 μ m) was encapsulated inside two spin-on polyimide layers ([10] Christiaens et al. , 2010; [15] Wang et al. , 2012). The result of this UTCP process is a very thin and flexible chip package, with a total thickness of around 50 μ m.
On the basis of previous work, an interesting further development of UTCP is to stack individual packages. A stack of two UTCPs cannot only increase the functional density, but also minimize mechanical bending stress in ultra-thin chips ([11] Endler et al. , 2011). However, in the fabrication of UTCP, the top spin coated polyimide film follows the shape of the embedded chips and creates a non-flat surface. The non-flat topography, in turn, leads to high pressure on the embedded chips during the stack lamination process, which results in die cracking and yield loss ([14] Priyabadini et al. , 2011). Thus, UTCP with a flat top surface (flat UTCP) is a key to reduce pressure on the...