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Proposed is a pseudo open drain output driver without external resistors. The resistance variation detector can reduce the cost and space of external resistors. The PVT variation detector is able to sense process, voltage and temperature conditions. The on-die termination impedance is constantly matched in response to the resistance, process, voltage and temperature conditions. The overall circuit occupies 0.126 mm^sup 2^ and consumes 5.58 mW, and the circuit is implemented in 0.18 µm CMOS technology.
Introduction: An output driver that controls slew rate using several VCO delay cells for a PLL structure was suggested in [1]. The PLL, however, may suffer from PVT variations leading to stability issues. In addition, the PLL locking time is relatively long, the area of the PLL is large and it dissipates a large amount of power. The speedlocked loop (SLL) is also one of the solutions [2]. As it has a closed loop, its lock time is relatively long. Moreover, designing a DCO with good linearity against PVT variations is difficult. An output driver that controls its slew-rate using a PVT variation detector was introduced in [3]. It is also a fully digital circuit, and takes only a single-cycle to adjust slew rate in the relatively constant range under PVT variations. However, as it cannot detect passive resistor variations in the output driver, this circuit may have a large error if used in a pseudo open drain (POD).
In these works, the output impedance of the output driver can be automatically matched to the applied load by comparing the input and output voltages of the output driver. A circuit that uses the linearity of the PMOS is introduced to avoid nonlinearities of MOSFETs [4]. However, they are not suitable for high-speed circuits and consist of analogy blocks that can be easily deteriorated by noise. In addition, they need external resistors. Another simple and full digital circuit was proposed in [5]. A critical disadvantage of this circuit, however, is that it cannot continuously control...