SnS/MoS2 van der Waals heterojunction for in-plane ferroelectric field-effect transistors with multibit memory and logic characteristics

Abstract

Ferroelectric two dimensional (2D) materials hold great potential to develop modern miniaturized electronic and memory devices. 2D ferroelectrics exhibiting spontaneous polarization in the out-of-plane direction have been extensively investigated to date, but the loss of their polarization during device operation has been problematic. Although 2D materials with in-plane ferroelectric behavior are more stable against depolarization and thus promising for memory and logic applications, experimental realization of in-plane 2D ferroelectric devices is still scarce. Here, we demonstrate in-plane ferroelectric field effect transistors (FETs) based on a van der Waals heterojunction (vdWHJ), which can perform multibit memory and logic operations. Tin monosulfide (SnS), a 2D material with in-plane ferroelectricity, is partially stacked on top of a semiconducting molybdenum disulfide (MoS2) on a silicon dioxide (SiO2)-coated silicon substrate to fabricate vdWHJ FETs in back-gate configuration. Switching of the in-plane polarization direction in the SnS channel modulates the contact barriers at the electrode/SnS and SnS/MoS2 interfaces, thereby creating high resistance states and low resistance states (LRS). The device exhibits a logic transfer characteristic with a high drain current on/off ratio (>106) in LRS and non-volatile memory performance with excellent retention characteristics (extrapolated retention time > 10 years). With exquisite tuning of the channel resistance by SnS polarization and gate bias, we realize multiple states with distinct current levels for multibit memory and logic operations suitable for programmable logic-in-memory applications.

INTRODUCTION

Ferroelectric materials have drawn significant attention for non-volatile memory (NVM) devices because they exhibit bistable electric polarization states that can be switched by an external electric field.¹ Although commercial ferroelectric NVM devices are based on a ferroelectric capacitor for information storage and a transistor connected in series, such device architecture is limited by the destructive readout process.^2,3 Ferroelectric field effect transistors (FeFETs), where a ferroelectric film is directly integrated as the gate dielectric of the FET to modulate the channel conductance, can address this challenge and are also advantageous for device downscaling.² Conventional FeFETs are based on perovskite oxide ferroelectrics such as barium titanate and lead zirconium titanate, but these materials exhibit poor retention characteristics when they are scaled down to ultrathin thicknesses because of large depolarization fields.⁴ Recently, two-dimensional (2D) van der Waals (vdW) ferroelectrics have gained considerable attraction because of their atomically thin nature and stable ferroelectricity compared to their bulk counterparts.^5,6 In addition, they can form vdW heterojunctions (vdWHJ) with other 2D materials to fabricate ultrathin devices without interfacial dangling bonds.⁷ Various 2D ferroelectrics with in-plane, out-of-plane, and intercorrelated⁸ ferroelectricity have been explored and reported for FeFET,⁹ ferroelectric memristor,¹⁰ ferroelectric tunnel junction,¹¹ spintronics,¹² and valleytronics.¹³ Toward the development of ultrathin FeFETs for NVM applications, out-of-plane 2D ferroelectrics have been intensively investigated as a gate dielectric layer while 2D semiconductors such as molybdenum disulfide (MoS₂) have been used as a channel.^14–17 Different engineering approaches were also implemented to increase the memory and retention characteristics, minimize the depolarization field, and program the device for other applications.^15,16 Despite the continuous improvement in the performance of FeFETs, suppressing gate leakage and depolarization field and improving data retention characteristics are still challenging in miniaturized devices.^18,19

In-plane 2D ferroelectrics exhibit superior performance in preventing the depolarization field compared to out-of-plane and intercorrelated ferroelectrics. Because the spontaneous polarization is confined in the 2D plane and each of the 2D layers are separated by the vdW gaps, these ferroelectrics are stable against out-of-plane perturbations and show significant ferroelectricity even at reduced thicknesses.^20,21 Also, owing to insufficient screening, the in-plane polarization can induce strong band bending near interfaces such as material junctions or ferroelectric domain-walls.²² Orthorhombic group-IV monochalcogenides (MX: M = Sn/Ge, and X = S/Se) have attracted substantial interest because of their purely in-plane ferroelectricity with large spontaneous polarization (P_S = 1.81–4.84 × 10⁻¹⁰ Cm⁻¹)^23,24 and remarkable piezoelectric coefficients (d₁₁ = 75–251 pmV⁻¹).²⁵ Among the various MXs, Tin Monosulfide (SnS) has shown promising characteristics for NVM devices because of its high chemical stability^26,27 and high curie temperature.²⁸ SnS also shows semiconducting properties and therefore can be potentially incorporated as a channel to realize unconventional NVM device architectures. In particular, when a van der Waals heterostructure of SnS and another 2D semiconductor is used as a channel of a FET, the barrier heights at the electrode–ferroelectric (M–Fe) and ferroelectric–semiconductor (Fe–S) junctions would be modulated by in-plane polarization switching in the SnS layer for channel conductance modulation. In addition to the barrier height control at the M–Fe and Fe–S interfaces, the semiconductor region near the Fe–S junction could be switched between accumulation and depletion of majority carriers as a result of the ferroelectric field effect.²⁹ Accordingly, the electrons would experience an additional barrier over the space charge region when the semiconductor surface is depleted due to ferroelectric polarization reversal.³⁰ Although various vdWHJ devices have been fabricated and tested, there is still a lack of systematic investigation of the in-plane Fe–S junction and the effect of in-plane ferroelectricity on the channel current modulation for FeFETs.

In this work, we report novel back-gate FeFETs based on vdWHJ of SnS and 2D semiconductor. Few-layer MoS₂ was used as a 2D semiconductor because of its excellent carrier mobility, high on/off current ratio, and good subthreshold swing for n-channel FETs.³¹ In addition to the source and drain electrodes at SnS and MoS₂ ends of the channel, a local contact was formed on the SnS/MoS₂ stack region to define the in-plane polarization across the SnS layer. By changing the polarization direction, we could modulate the contact barriers at the M–Fe and Fe–S junctions to realize high and low resistance states. The device showed a high current on/off ratio (>10⁶) with excellent data retention and endurance characteristics for logic and memory applications. Benefiting from the back-gate configuration of the fabricated FeFET, we could precisely control the drain current characteristics by in-plane polarization state of SnS and electrostatic gating to achieve the multibit memory and logic operations.

RESULTS AND DISCUSSION

Figure 1A schematically illustrates the structure of our back-gate FeFET based on the SnS/MoS₂ vdWHJ. First, a MoS₂ flake was mechanically exfoliated and stacked on a Si substrate coated with a SiO₂ gate dielectric layer (thickness: 285 nm). A mechanically exfoliated SnS flake was then partially stacked on MoS₂ to fabricate a vdWHJ, followed by the formation of an electrode on SnS in the vdWHJ region. This local contact was used to apply an external voltage across the SnS layer (V_SnS) to control the in-plane polarization. Electrodes were also deposited on the SnS and MoS₂ regions away from the vdWHJ to create a source and drain. An atomic force microscope (AFM) image of a typical FeFET device is presented in Figure 1B. Electrodes were deposited on each SnS, MoS₂, and SnS/MoS₂ heterojunction area with careful contact arrangement to obtain SnS FET (terminals 1 and 2), MoS₂ FET (terminals 6 and 7), and SnS/MoS₂ FeFET (terminals 2, 3, and 5) in a single structure. For the SnS/MoS₂ FeFET, terminal 3 acts as the local contact to apply V_SnS, while terminals 2 and 5 function as the source and drain contacts, respectively. The complete fabrication process, an optical microscope (OM) image of the device, and structural specifications are also presented in Supporting Information Section 1 (Figure S1–S3). Based on the literature on electronic band structures of SnS and MoS₂ (Figure S4, Supporting Information Section 2), we deduced that a type II (staggered) heterojunction would form at the SnS/MoS₂ interface, where the conduction band minimum (CBM) and valence band maximum (VBM) of MoS₂ lie below the CBM and VBM of SnS, respectively (Figure 1C). When a negative bias is applied to the local contact (V_SnS <0), the ferroelectric polarization in the SnS layer points to the Fe–S junction, which develops positive and negative bound charges at the Fe–S and M–Fe junctions, respectively (Figure 1C, case (i)). As a result, electronic bands in the SnS layer will bend downward (upward) close to the Fe–S (M–Fe) interfaces. Because of the semiconducting properties of SnS, mobile charges will screen the polarization bound charges of the opposite signs and confine the band bending near the two interfaces. The positive bound charges at the Fe–S junction will also result in downward band-bending in the MoS₂ region, which will be confined in the vicinity of the interface because of charge screening by negative mobile charges in MoS₂. These polarization-induced changes in the electronic bands will modify the potential barriers within the FeFET. At the M–Fe junction, the Schottky barrier height (Φ_B) will be increased by the upward band-bending, which will impede electrons to flow from metal to ferroelectric. Electron transport from SnS to MoS₂ will also be hindered by the built-in electric field at the Fe–S junction, which results from the positive bound charges in SnS and the negative mobile charges in MoS₂. Accordingly, the device will be in a high resistance state because electrons will experience a higher resistance compared to the case where SnS is not polarized when they are directed from the source to drain terminals. When the ferroelectric polarization switches to the opposite direction (pointing to the M–Fe junction) by applying a positive bias to the local contact (V_SnS >0), changes in the band structure become more favorable for the electron transport from source to drain (Figure 1C, case (ii)). At the M–Fe junction, positive bound charges will bend the conduction band downward and decrease the Schottky barrier height. In addition, the built-in electric field generated by the negative bound charges in SnS and the positive mobile charges in MoS₂ at the Fe–S junction will promote the flow of electrons toward the drain terminal. Because of these changes in the band structure, the device will be in a low resistance when the polarization points to the M–Fe junction.

FIGURE 1. Device architecture of the SnS/MoS2 vdWHJ FeFET and work function measurement. (A) Schematic illustration of the SnS/MoS2 vdWHJ FeFET fabricated on a 285 nm SiO2/Si substrate. Source and drain contacts were formed on the SnS and MoS2 flakes, respectively. The local contact was also introduced on the vdWHJ to apply a voltage across the SnS layer (VSnS) and define its polarization state. (B) Atomic force microscopy (AFM) image of a typical SnS/MoS2 vdWHJ FeFET. Multiple contact terminals were fabricated to realize three types of FETs on a single heterostructure: SnS FET (terminals 1 and 2), MoS2 FET (terminals 6 and 7), and SnS/MoS2 FET (terminals 2, 3, and 5). (C) Proposed energy band diagrams of the SnS/MoS2 vdWHJ FeFET under two different polarization states at zero drain voltage. (D) Scheme describing the KPFM measurement set-up. (E) AFM image of the SnS/MoS2 heterostructure for KPFM analysis. (F) Surface potential profiles along the SnS/MoS2 heterostructure in three states: (1) pristine state, (2) polarization direction of SnS toward MoS2 (VSnS = −20 V) across SnS, and (3) polarization direction of SnS away from MoS2 (VSnS = +20 V).

We investigated the effect of the in-plane polarization state on the surface potential across the SnS/MoS₂ heterostructure based on Kelvin-probe force microscopy (KPFM). For the KPFM measurements, the SnS and MoS₂ flakes were stacked on top of a gold substrate such that a bias voltage can be applied across the junction without an electrical short (Figure 1D). The OM image of the KPFM sample and film thickness data are presented in Supporting Information Section 3 (Figure S5–S6). Figure 1E shows an AFM image of the stack arrangement for KPFM measurement. External voltage pulses were applied across the contact electrodes to define the polarization states of SnS. The surface potential was measured under three states of ferroelectric polarization: (1) pristine, (2) polarization direction toward MoS₂, and (3) polarization direction away from MoS₂. In the first state, the measurement was carried out immediately after sample fabrication without applying any voltage across the SnS layer. In the second state, a +20 V pulse voltage was applied at the SnS terminal with the MoS₂ terminal grounded (equivalent to V_SnS = −20 V) to generate a spontaneous polarization in the SnS layer pointing toward MoS₂. In the third state, a −20 V pulse was applied at the SnS terminal (equivalent to V_SnS = +20 V) to switch the polarization direction toward the SnS/metal junction. The surface potential profiles measured under three different states are presented in Figure 1F. In all cases, MoS₂ exhibits a lower potential than SnS because of its higher work function. For the pristine case, we noted that the surface potential in the heterojunction region was lower compared to that in the SnS area because of the built-in electric field at the SnS/MoS₂ junction resulting from the Fermi level alignment. For the case where the polarization of SnS points toward the MoS₂ layer, the surface potential in both SnS and heterojunction regions became lower compared to the pristine state because of positive bound charges formed at the SnS/MoS₂ junction. The opposite phenomenon was observed when the SnS polarization direction was reversed, where the surface potential became higher due to the negative bound charges at the junction.³² Additional surface potential mapping and profile data from the same flake arrangement measured at different points are also presented in Supporting Information Section 4 (Figure S7).

To confirm the lattice structure, phase, and crystal quality of the SnS and MoS₂, we performed Raman spectroscopy of the flakes on the SiO₂/Si substrate at room temperature (Figure 2A). The SnS flakes showed high intensity peaks at 98 ± 1 and 224 ± 4 cm⁻¹, which correspond to the A_g mode arising from the interatomic vibration between the Sn and S atoms.^33,34 Additionally, we observe a peak at 302 ± 1 cm⁻¹, which can be attributed to the intralayer vibration of the S-S bonds.^33,35 This spectral feature indicates that a secondary tin sulfide phase, Sn₂S₃, was also present in our SnS layer.^33,35 The Raman spectrum from MoS₂ flakes was characterized by high intensity peaks at 380 ± 1 and 405 ± 1 cm⁻¹, which correspond to the in-plane (${\mathrm{E}}_{2\mathrm{g}}^1$) and out-of-plane (A_1g) vibration modes, respectively.³⁶ No other secondary phases were observed in the MoS₂ Raman spectra, thus confirming the high crystal quality of MoS₂ flakes used in the experiments.³⁷ For the case of SnS/MoS₂ heterojunction, individual SnS and MoS₂ Raman peaks were clearly visible, indicating proper van der Waals stacking without any imperfections. The ferroelectric properties of SnS flakes were also investigated by using lateral piezo response force microscopy (PFM). The sample preparation details are presented in Supporting Information Section 5 (Figure S8). Figure 2B shows the lateral PFM phase, lateral PFM amplitude, and topography images of the SnS flake stacked on the gold substrate. The in-plane phase and amplitude characteristics can be observed in the presented data. PFM images reveal that certain domains (dark color in phase and light color in amplitude) give larger PFM signals than others, which is due to the inhomogeneous surface morphology, as reflected in the topography image. Figure 2C presents the representative single point PFM amplitude and phase data measured with the tip voltage of 5 V. A well-defined butterfly shaped loop in the lateral PFM amplitude plot and a lateral PFM phase shift of 180° with respect to the applied DC bias confirms the strong in-plane ferroelectricity in the SnS flake.

FIGURE 2. Structural characteristics of SnS and MoS2 flakes. (A) Raman spectra of SnS, MoS2, and SnS/MoS2 stack measured at room temperature using a laser excitation wavelength of 532 nm. (B) Lateral PFM phase, amplitude, and topography images of the SnS flake. The measurement was performed under a DC bias of 5 V. The PFM contrast indicate the presence of ferroelectric domains. (C) Lateral PFM amplitude and phase as a function of DC bias obtained from the single point PFM spectroscopy of SnS. The DC bias was applied in the bidirectional sweep mode as follows: 0 V ⟶ 5 V ⟶ 0 V ⟶ -5 V ⟶ 0 V.

To further investigate the in-plane ferroelectric response of the SnS film, a memristor with symmetric Ti/Au electrodes was fabricated (Figure 3A–B). We used Ti as a low work function metal (ϕ ≈ 4.33 eV) to create ohmic-like contacts on the SnS layer (ϕ ≈ 4.9 eV). It was expected that the ohmic contacts will show minimal impact on the memristor response upon polarization switching as compared to the Schottky contacts. With the drain (source) electrode biased (grounded), pinched hysteresis loops were observed in I-V_DS curves during the round sweeps of V_DS from positive (negative) to negative (positive) voltages because of the in-plane polarization of SnS (Figure 3C). The device exhibits a slight asymmetric current–voltage (I-V_DS) characteristic with one order difference in current level at the maximum tested positive and negative voltages (V_DS = ±90 V), most likely because of the difference in contact areas at the source and drain.³⁸ The pinched hysteresis loops are the characteristic of the ferroelectric memristive behavior, which involves switching between high and low resistance states (HRS and LRS).³⁹ As indicated by the arrows, the device was under LRS when the drain bias was swept from the maximum negative voltage (−V_{DS, max}) to 0 V, at which the device switched from LRS to HRS. The device maintained its HRS during the drain bias sweep from 0 V to the maximum positive voltage (+V_{DS, max}), and then attained LRS as the sweep voltage reaches +V_{DS, max}. When the sweeping direction was reversed (from +V_{DS, max} to −V_{DS, max}), the device maintained its LRS till 0 V, switched to HRS for the further sweep, and then returned to LRS at −V_{DS, max}. The device demonstrated a large switching ratio between the HRS and LRS of ~10² at a certain voltage bias (−23 V). The memristive characteristic of the device was further demonstrated by conducting repeated poling using ±60 V drain voltage sweeps. The resistance (R) values of HRS and LRS were measured at V_DS = −23 V to evaluate the memristive behavior (Figure 3D). Over the 30 poling cycles, the device exhibited reproducible switching between HRS and LRS, which indicates that the resistive switching by the switching of in-plane ferroelectric polarization in the SnS layer was reversible.

FIGURE 3. Device characteristics of the SnS ferroelectric memristor. (A) Schematic illustration of the device structure. (B) An OM image of the device. (C) Hysteretic |I|-VDS loops of the device measured with different VDS, max. (D) Switching of the device resistance (R) measured at VDS = −23 V over 30 poling cycles.

Taking advantage of the memristive switching behavior of the SnS, we realized the in-plane FeFET based on the SnS/MoS₂ vdWHJ as depicted in Figure 1B. The effect of in-plane polarization of SnS on the FeFET characteristics was investigated by performing the current–voltage measurements in two steps. First, we applied a V_SnS pulse of +20 V for 1 s across the SnS layer (terminals 2 and 3) to set the polarization direction toward the M–Fe junction, followed by the gate and drain voltage sweeps (terminals 2 and 5) to obtain the transfer and output characteristics. In the second step, a V_SnS pulse of −20 V was applied for 1 s to reverse the polarization state of SnS, and then the transfer and output curves were measured. Figure 4A shows the transfer characteristics of the SnS/MoS₂ FeFET under two different SnS polarization conditions. As expected from the memristive behavior of SnS, the device exhibited distinct states depending on the polarization direction. When the SnS polarization was pointing toward the source terminal (V_SnS = +20 V), the device showed a high on-state current of 26 nA with an on/off ratio exceeding 10⁶ (black curve). The small hysteresis in the transfer curve was attributed to the extrinsic/environmental effects and charge traps near the interface between SiO₂ and SnS/MoS₂.^40–42 The on-state current was reduced by one order of magnitude to 3.5 nA when the SnS layer polarization direction was reversed (V_SnS = −20 V, red curve). A similar polarization-dependent behavior was observed in the device output response, where the drain current level was higher for the SnS polarization aligned toward the source terminal (Figure 4B). We also characterized the current–voltage characteristics of SnS FET (terminals 1 and 2) and MoS₂ FET (terminals 6–7) (Figure S10–S11, Supporting Information Section 6). Both devices showed approximately two orders of lower magnitude in drain current on/off ratios (on the order of 10⁴) compared to SnS/MoS₂ FET, which highlights the advantage of our heterojunction system. The transfer and output curves of the SnS/MoS₂ FET for V_SnS of different magnitudes are also presented in Supporting Information Section 7 to show the effect of SnS polarization on the device behavior (Figure S12–S13).

FIGURE 4. Electrical behavior of the SnS/MoS2 FeFET. (A) Transfer characteristics of the device under bi-directional gate voltage sweeps from −25 to 25 V (VDS = 0.1 V) for two different polarization states of SnS obtained by applying VSnS of +20 V (black curve) and − 20 V (red curve). (B) Output characteristics of the device under a drain voltage sweep from −1 to 1 V (VGS = 10 V). Black and red curves represent the drain currents after applying VSnS = 20 V and VSnS = −20 V, respectively. (C–E) Energy band diagrams of the device at different SnS polarization states under a positive drain voltage. (C) pristine state, (D) SnS polarization directed toward the source terminal, and (E) SnS polarization directed toward the SnS/MoS2 junction.

To reveal the operation mechanism of the SnS/MoS₂ FeFET, we constructed the energy band diagram of the device based on the band gaps, work functions, and KPFM surface potential measurements (Figure S14–S15, Supporting Information Sections 8 and 9). Based on the surface potential difference between the MoS₂ and SnS regions, we confirmed that the type II heterojunction formed at the SnS/MoS₂ interface with the CBM of SnS placed higher than that of MoS₂. The energy band diagrams under three different polarization states (pristine, V_SnS >0, and V_SnS <0) at zero drain bias are presented in Figure S15, which are consistent with those we initially proposed in Figure 1C. When a positive drain voltage is applied to the device (V_DS >0), the energy bands bend downward from source to drain because of the external electric field (Figure 4C–E). Compared to the case without the SnS polarization (Figure 4C), the device will exhibit a lower Schottky barrier at the M–Fe junction for electron injection when the SnS layer is polarized toward the source terminal (Figure 4D). The reduced Schottky barrier is attributed to the downward band-bending induced by the positive bound charges in SnS near the M–Fe interface. In addition, the built-in electric field at the Fe–S junction resulting from the negative bound charges in SnS and positive mobile charges in MoS₂ will also promote the electron transport toward the drain terminal. Therefore, the device is under LRS exhibiting higher current levels compared to the pristine state. For the case where the SnS polarization aligned toward the MoS₂ layer (Figure 4E), the Schottky barrier at the M–Fe junction becomes higher because of the upward band-bending induced by the negative bound charges in SnS. The built-in electric field at the Fe–S junction (due to the positive bound charges in SnS and negative mobile charges in MoS₂) also impedes the electron transport, thereby resulting in HRS with lower current levels.

Multi-valued current–voltage behavior and multibit storage capacity are highly desirable for processing a large amount of data and achieving device downscaling. As a proof-of-concept demonstration, the vdWHJ FeFET has been investigated for multibit logic operation by programming the SnS polarization state and electrostatic gating (Figure 5). To this end, we investigated the time evolution of drain current (I_DS vs t) for different combinations of V_SnS and V_GS. The drain voltage was kept small (V_DS = 1 V) to avoid unintentional switching of SnS polarization during the measurement. Figure 5A shows the current response of the device at V_GS = 20 Vand when V_SnS pulses (pulse width: 1 s) of different magnitudes and directions (1, −1, 5, −5, 10, −10, 20, and − 20 V) were sequentially applied. The current level did not change for the initial V_SnS of 1 and −1 V because V_SnS was lower than the coercive voltage of SnS. As V_SnS increased further to 5 V and above, the difference in drain current level under two SnS polarization states become evident especially for high V_SnS. For example, I_DS values were 2.2 × 10⁻⁸ and 8.9 × 10⁻⁹ A for V_SnS of +10 and −10 V, respectively, which changed to 3.8 × 10⁻⁸ and 6.8 × 10⁻⁹ A after applying V_SnS of +20 and −20 V. Because the carrier concentration in 2D semiconductors can be modulated by electrostatic gating, we could also realize multiple drain current levels by changing V_GS. The effect of V_GS on the current response is presented in Figure 5B and S16 (Supporting Information Section 10). The results confirm that the SnS poling and gate modulation establishes two degrees of freedom in defining the device's operational characteristics. The SnS polarization state defines the memory function (i.e. bit ‘0’ or ‘1’), and the gate-controlled current level defines the device logic operation. The current level can be fine-tuned by the SnS polarization state and gate voltage to establish a multibit memory and logic characteristics as well.

FIGURE 5. Multilevel logic and memory characteristics of the SnS/MoS2 FeFET. (A) Drain current after applying VSnS pulses of different signs and magnitudes (1, −1, 5, −5, 10, −10, 20, and − 20 V). The current was measured after each VSnS pulse at gate and drain voltages of 20 and 1 V, respectively. (B) Drain current measured at different gate voltages (VGS = 0, 5, and − 5 V) after applying different VSnS pulses (10, −10, 20, and − 20 V). Drain voltage was fixed at 1 V. (C) Retention characteristics of the device after applying VSnS of +20 and − 20 V (VGS = 10 V and VDS = 1 V). (D) Endurance characteristics of the device for cyclic VSnS pulses of ±10 V (pulse width: 1 s, pulse delay: 1 s). Gate and drain voltages were 10 and 1 V, respectively.

To investigate the memory characteristics of the vdWHJ FeFET, the retention properties were measured under two polarization states formed by applying V_SnS of ±20 V, while V_DS and V_GS were fixed at 1 and 10 V, respectively (Figure 5C). Each state was stable for more than 10⁴ s and exhibited a nearly constant drain current level. The results indicate that the in-plane polarization states of SnS are stable and their retention time can be further extrapolated to 10 years. Endurance properties of the device were also evaluated by measuring I_DS when cyclic V_SnS pulses of ±10 V were applied (pulse width: 1 s, pulse delay: 1 s) (Figure 5D). The current after each V_SnS pulse was obtained by applying a drain voltage pulse of 1 V. The device was tested for more than 10⁴ s, which corresponds to more than 2000 polarization switching cycles. Stable drain current characteristic measured after every polarization switching cycle indicates excellent polarization-dependent drain current modulation and superior endurance characteristics.

CONCLUSIONS

In conclusion, we have presented a proof-of-concept FeFET architecture based on the SnS/MoS₂ vdWHJ. The channel current can be effectively tuned by the in-plane ferroelectricity (polarization) of SnS, which modulated the contact barriers at junctions. Due to different work functions and bandgaps of the two semiconducting layers, a built-in potential barrier was observed at the SnS/MoS₂ junction, which facilitates the spatial separation and migration of charge carriers generated by the applied electric field. The device showed efficient charge conduction through the heterojunction with the current on/off ratio of >10⁶. The SnS layer can maintain its polarization state for more than 10⁴ s which can be extrapolated to the data storage for more than 10 years. The device with switchable and stable polarization state and high current on/off characteristics make our work promising for programmable logic-in-memory applications.

EXPERIMENTAL SECTION

Device fabrication: The SnS/MoS₂ vdWHJ device fabrication was carried out by implementing the dry transfer technique. The SnS and MoS₂ flakes were mechanically exfoliated from the commercial bulk crystals (2D semiconductors, USA) using scotch tape. The MoS₂ flake was first transferred onto the 285 nm SiO₂/Si substrate followed by stacking of the SnS flake. The flake selection was carried out under an optical microscope (Olympus BX53M) and the transfer process was assisted by a polydimethylsiloxane (PDMS) film in the nitrogen ambient inside a glove box. The electrode patterns were designed using AutoCAD, and electron-beam (e-beam) lithography was carried out to transfer the CAD patterns on the samples using a polymethyl methacrylate (PMMA) film as an e-beam resist layer. The metal electrodes were formed by sequentially depositing Ti (10 nm) and Au (60 nm) using an e-beam evaporator, followed by lift-off of the resist.

Characterization: The film thickness, work function, and piezoelectric properties were measured using an atomic force microscope (Park-NX10). The Raman spectra analysis was carried out at room temperature using the WITEC Alpha 300 M system with a 532 nm laser source to investigate the structural characteristics. The electrical properties were measured in a vacuum probe station, and the data was recorded using a Keithley 4200 semiconductor characterization system.

AUTHOR CONTRIBUTIONS

Prashant Singh and Dongjoon Rhee led the experimental work with support from Sungpyo Baek, Hyun Ho Yoo, Jingjie Niu, Myeongjin Jung and wrote the original draft. Joohoon Kang and Sungjoo Lee conceived the ideas as supervisors and wrote and revised the paper.

ACKNOWLEDGMENTS

Prashant Singh and Dongjoon Rhee contributed equally to this work.

FUNDING INFORMATION

This study was supported by a National Research Foundation of Korea (NRF) grant funded by the Korean Government (MSIT) (2022R1A2C3003068, 2022M3F3A2A01072215, 2020M3F3A2A03082047, 2020R1C1C1009381). This work was supported by Samsung Electronics Co., Ltd (IO201215-08197-01).

CONFLICT OF INTEREST STATEMENT

The authors declare no conflict of interest.

SUPPORTING INFORMATION

Supporting Information is available from the Wiley Online Library or the author.