Tessent BSCAN Insertion on 28nm SOC

Abstract

The testing plays a vital role to ensure the correctness of chip functionality. Boundary scan is a structured design-for-test technique, which makes digital I/O pins testable by means of inserting boundary scan cells between core logic and pins. It enhances chips accessibility and testability. This project has implemented the Boundary scan on 28 nm SOC having approximated 5 million gate counts. Total pin count of SOC is 107. The project work is done on Linux platform. Tcl scripting language is used for setting parameters for design and placing runs on servers. File manipulations are done in Vi editor. BSCAN is done using Tessent BSCAN tool from Mentor Graphics. The simulations are carried out on NC Verilog simulator from Cadence. The outcome of project is, Gate level Netlist with BSCAN architecture inserted. The BSCAN cells inserted have length of 146. To cover entire SOC, the scan insertion and MBIST can be performed.

Headnote

Abstract

The Testing plays vital role to ensure the correctness of chip functionality. Boundary scan is a structured design-for-test technique which makes digital I/O pins testable by means of inserting boundary scan cells between core logic and pins. It enhances chips accessibility and testability. This project has implemented the Boundary scan on 28 nm SOC having approximated 5 million gate counts. Total pin count of SOC is 107.The project work is done on Linux platform. Tcl scripting language is used for setting parameters for design and placing runs on servers. File manipulations are done in Vi editor. BSCAN is done using Tessent BSCAN tool from Mentor Graphics. The simulations are carried out on NC Verilog simulator from Cadence. The outcome of project is, Gate level Netlist with BSCAN architecture inserted. The BSCAN cells inserted have length of 146. To cover entire SOC, the scan insertion and MBIST can be performed.

Keywords

Boundary Scan (BSCAN), S°C, Mentor Graphics, Tcl (Tool command language).

1. Introduction

Design for Test ("Design for Testability" or "DFT") is a name for design techniques that add certain testability features to a chip. The purpose of manufacturing tests is to validate that the product hardware contains no defects that could, otherwise, adversely affect the products correct functioning. Testing has two major aspects: control and observation. To test any system it is necessary to put the system into a known state, supply known input data (test data) and observe the system to see system to see if it performs as designed and manufactured. If control or observation cannot be carried out, there is no way to know empirically if the system performs as it should [1].

Boundary scan is a structured design-for-test technique, standardized as IEEE 1149.1 standard. In Boundary scan, a scan shift-register stage is placed adjacent to every input or output pin of the chip i.e.at the component boundaries. These shift registers are nothing but the boundary scan cells.

The cells are connected around the periphery of the IC, which forms the boundary scan path. Data can flow directly through the boundary-scan cell when normal operation of the component is required [2]. During testing, the cells at output pins can be used to drive signal values onto the external network, while those at the input pins can capture the signals received.

2. Background & Relevance

High-volume product lines require a high level of confidence in the components before final system assembly. Most system manufacturers find it too expensive and difficult to completely test an assembled system on the manufacturing floor. It is also virtually impossible to measure test coverage of the functional system tests used in manufacturing. Even if systems could be tested exhaustively, it is a major challenge to identify and replace faulty boards or components. Therefore, as chips and boards get increasingly complex, adequate testing of the chips and boards is mandatory. While it is easier to test the components stand-alone before system assembly, the cost of a defective component that enters the manufacturing process can be high and will increase in proportion to how late in the process the component is identified and replaced [3].

If the limited tests in manufacturing do not identify the defective component, the system may be shipped to a customer, in which case the cost of the defect can be very high indeed when the component finally exhibits the failure mechanism. The manufacturing process thus places the bulk of the test burden at the component level and relies on high quality component tests for overall success. Clearly, the components (both chips and boards) need to be highly testable in order for the system to be manufacturable in volume. Manufacturing testing enables development teams to screen devices for manufacturing defects.

Boundary scan technique covers for stuck-at, interconnects, open and shorts type of faults for digital I/O pins of the chip. It offers the controllability by facilitating the internal input nodes handling with primary inputs and offers observability by facilitating the internal output nodes handling with primary outputs [4].

3. Boundary scan details

This project covers complete boundary scan on SOC which will be manufacture using 28 nm Technology. The Gate count is around 5 million. To perform boundary scan the Tessent tool undergoes a particular flow. The flow is as follows:

ETChecker-clocks

This step extracts the information of the RTL design along with clock architecture. It provides the details of clock network graphically as well as specifies properties that includes the parameters viz. functional frequency, label etc. ( Values are to be entered by DFT engineer)[5]. The table after each step describes generated files and directories:

ETChecker-Rules

It checks for design rules to ensure that your circuit is free of violations and meeting embedded test requirements described in RTL Description Requirements. This run requires several iterations to identify and correct the design aspects that do not meet the requirements for implementing Mentor Graphics Embedded Test [5].

Run-ETPlan-gen

The ETPlanner uses etCheckerInfo file and other optional files such as .LVICTech File, .ET-Defaults File, .CADSetup File and DEF or PDEF Files to generate my design.etplan file. This file describes the embedded test requirement plan for chip. The generated plan provides a correct by construction embedded test plan for the design based on the user- defined requirements [6, 8].

Make-checkplan

In this mode, ETPlanner uses the .etCheckerInfo file and the .etplan file to check the embedded test plan against embedded test compatibility rules and generate a report (ET Summary) that provides information related to test time and power requirement for the embedded test plan. This report also provides all warning associated with the .etplan file content [6, 8].

Gen-LVWS

In this mode, ETPlanner uses the .etplan file (generated with mode GenPlan) and the .etCheckerInfo file to generate Mentor Graphics embedded test environment that contains the directory structure recommended for the automation of the embedded test generation and verification, make targets, configuration files, etc. The .etCheckerInfo and .etplan files are mandatory for this mode [6, 8].

Embedded-test

This step is performed using make Embedded-test target. It makes use of my design.etassemble file generated by ETPlanner. It generates the TAP RTL for your design. Also the scripts to convert RTL to Gate level Netlist [7,8].

Designe

This step involves generating test benches for verification and performing simulation. The testbenches generated by ETVerify at this stage verify all types and instances of embedded test controllers in the given physical region. It performs the rule check and generates Test Connection Map file [7, 8].

Edit-synthesis-script

It modifies or updates the scripts written in step 6, to make scripts compatible with test mode specified. For my project it keeps only BSCAN related [7].

Make-synth

This optional make target synthesizes all embedded test controllers which were generated by ETAssemble [7].

Concatenate-Netlist

It merges top level Netlist with Netlist containing TAP. Then it generates a single top level Netlist with DFT inserted in it [8].

Config-etsignoff

This make target runs ETVerify to create the .etSignoff configuration file. This file defines testbench configuration for design. It contains a list of test steps which is required to perform early verification of all embedded test features on design [8].

Lvdb-prelayout

It generates a pre-layout Logic Vision circuit database. The pre-layout LVDB is stored in the ETSignOff Directory. This ensures that within only the ETSignoff directory, you will be able to sign off the final post-layout version of your chip [8].

Make-testbench

This make target runs ETVerify to create test benches for the verification of all embedded structures. For this it makes use of .signoff configuration file and the data from pre layout lvdb [8].

PostLV-MBIST-Edits

This step will update the Netlist to make some TAP connections and providing controllability for power control signals (LS (Light Sleep), DS (Deep Sleep), SD (Shut Down)) of the memories.

PostLV-BCAD-Edits

This step will update the Netlist to provide controllability to the pad input pins like PU, PD, DR0, DR1 etc. These changes are necessary for BSCAN simulations to work fine.

4. Simulation Results

After completing entire boundary scan flow, the simulation of design is carried with cadence ncverilog Simulator. Once simulation is completed the log file shows whether it is successful or done with violations. For my design initially there were 226 compare failures. These failures were removed by tracing schematic backwards from the point of failure occurrence. After locating root for failure, the MUXes with required logic are inserted at appropriate level [9]. Fig.1 depicts the schematic tracing window of cadence simulator and fig.2 depicts snapshot console window with successful simulation.

5. Conclusion & Future work

Design for Test (DFT) is important as functional verification cannot fully represent to detect manufacturing defects. My project has implemented the Boundary scan chain on S°C to be manufacture in 28 nm technology. For digital I/O pins, the outcome obtained is presented in table below.

After covering digital I/O pins, the scan insertion can be done on chip in order to cover entire combinational and sequential logic. This can be achieved by chaining sequential logic together as combinational logic couldn't be observed completely. The sequential cells adjecent to combinational logic can capture the data for testing. Once internal logic and I/O pins become testable, the memories can be made testable by means of MBIST i.e. Memory Built In Self-Test. Tessent tool can be used to insert complete testability to S°C.

References

References

[1] IEEE standard for reduced pin and enhanced functionality Test Access Port and Boundary scan architecture IEEE computer society, 2009.

[2] Mentor Graphics Embedded Test Hardware Reference Software version 9.1, August 2010.

[3] R G Ben Bennetts "Boundary scan tutorial" version 2.1, September 2002.

[4] Colin M. Maunder, Rodham E. Tulloss The test access port and boundary scan architecture IEEE computer society press tutorial.

[5] Mentor Graphics ETchecker usage guide and Reference Software version 9.1, August 2010.

[6] Mentor Graphics ETPlanner tool Reference Software version 9.1, August 2010.

[7] Mentor Graphics ETAssemble tool Reference Software version 9.1, August 2010.

[8] Mentor Graphics Tessent S°C Usage Guide Software version 9.3, February 2011.

[9] Cadence "Design Browser" Product version 11.1, March 2012.