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HSINCHU, TAIWAN - Dark clouds are hovering over the evolutionary path of personal-computer main memory. The 64-Mbit 100MHz synchronous DRAMswhich are supposed to be the bridge between today's fast EDO memories and tomorrow's Direct Rambus DRAM or SLDRAM chips-aren't yet shipping in volume, but they're already the focus of looming price pressure and technical criticism. By the time full production arrives, the 100-MHz SDRAM market may have already been stripped of its margins and torn by dissent about interface specifications.
For PC makers, the possibility of tumbling prices for fast SDRAMs is a dream come true, but ongoing debates over interfaces for those memories could become a nightmare.
The Jedec specification that was supposed to standardize the SDRAM interface has already proved to be amazingly subject to interpretation. In addition, EE Times has learned, Intel Corp. has been circulating a specification for its still-unannounced BX chip set that requires stricter timing than does Jedec. And the continuing debate between proponents of LV-TTL, HSTL, CTT and other electrical-interface specs has yet to be resolved.
OEMs are reporting interface differences even among the current, relatively slow SDR.AMs. The variations from one vendor to another are minor, but sufficient to force DRAM-controller designers to build a lot of programmability into their timing.
The problem is worse for memory-module vendors trying to meet the firm timing spec.
"We may have to qualify three or four types of chips in a given module," said Nahid Cassazza, product marketing manager for Kingston Technology Corp. (Fountain Valley, Calif.). "With synchronous DRAMs, we've extended our pre-release testing and made it more elaborate. The length of time we spend testing before releasing the product is much longer."
Different DRAM manufacturers implement the power-up mode and register-setting steps in different ways. Each manufacturer must prove that its SDRAMs operate with each of the major chip sets, and the NEC manager said "it is almost impossible" to get true compatibility for those functions.
Some observers blame Jedec for the current SDRAM compatibility problems, saying the group has been bogged down by too many pet proposals, a situation that has led to a loose set of specifications that the manufacturers can implement in different ways.
"Some companies have tried implementing the standard before it's complete, so it...