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San Jose, Calif. - Taking a cue from submicron cell-based ASICs, Altera Corp. has added a phase-locked loop (PLL) clock circuit to its Flex10k family of FPGAs. That will reduce clock-related delays enough, the company said, to improve system- clock frequency by 50 percent in some designs.
"Clock-timing issues intrude into system performance in two ways," said Craig Lytle, Altera's director of applications and product planning. "The clock delay plus the maximum clock skew adds to the register-to-output delay to determine the clock-to-output delay of the chip. More subtly, but just as importantly, we keep the register hold time no greater than 0 across the chip. That means we have to delay the data coming into the register by at least the sum of clock delay plus clock skew. That means, if you work through the arithmetic, that the clock skew is a term in the formula for the register set-up...