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Complex chips with large gate counts pose problems for design verification. Simulation run-times for such chips are measured in days or weeks, making it impossible to verify logic quickly, thoroughly or often enough. A potential solution lies in the technique of formal verification, the use of mathematical methods to prove functional equivalence between two design descriptions. This technology promises both thorough verification and shorter run-times.
Much has been written about the fact that today's ASIC and IC designs have become so large and complex that they're tough to build quickly and accurately. In particular, deep-submicron semiconductor technology has imposed new timing, power and modeling requirements upon logical- and physical-design tools.
The logic designs being created in deep-submicron chips now comprise hundreds of thousands of gates. Not only do these IC and ASIC designs-many of which are essentially systems (or large subsystems) on a chip-have more gates on a single die, but their underlying architectures and logic structures are far more complex as well.
Even as the logic has become so complex, designers are also forced to make more logic iterations than ever before. New designs almost always require insertion of extra test logic to overcome long test times.
Timing issues brought about by deep-submicron technology cause logic changes as well. Clock trees must now be separately synthesized, and it's often necessary to tweak the logic to correct timing problems after floor planning and again after layout.
One-two punch
The one-two punch of very complex designs and numerous iterations has made thorough verification more important than ever. But such complexity makes it virtually impossible to create complete vector sets. The result is a verification gap.
Even partial vector sets take so long to simulate that verification of each logic iteration is not possible. Thus designers often face a troubling choice: stretch out the design cycle by running enough vectors to be...