Floorplanning, RTL synthesis link up for chip-level interconnect

Claiming a new "design with physical" approach t hat helps solve problems with chip-level interconnect. Cadence Design Systems this week plans to announce a new component of its Cadence Logic Design Team Solution. It integrates the Encounter RTL Compiler synthesis tool with the First Encounter floorplanning tool so that synthesis can get timing estimates from physical floorplanning data.

The solution is aimed at the 10 percent of wires that represent chip-level interconnect. But that's no small matter, according to Cadence, because these long wires are the hardest to predict and show the greatest variations. Solutions already exist for timing prediction for the 90 percent of wires that represent local interconnect, such as Cadence's own physical layout estimation (PLE) technology, but the longer chip-level interconnect wires generally require placement...