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Portland, Ore. - Research into competing architectures fur the multicore processors of the future will take center stage this week when Intel Corp. demonstrates its Teraflop Research Chip-code-named Polaris-at the International Solid-State Circuits Conference in San Francisco. The 80-core chip crunches 1 trillion floating-point operations/second when running at a 3.2-GHz clock speed and consumes 62 watts, to yield a record 16 Gflops/ watt. And by cranking the clock up to 5.6 GHz, the chip bested 1.8 teraflops-that's 80 percent faster-albeit by increasing power consumption fourfold to 265 W, or 3.7 Gflops/W.
"Others are building massively parallel multicore chips, but with this research chip Intel is thinking outside the box," said Jim McGregor, who is principal analyst and research director of the Enabling Technologies Group at In-Stat. "Intel also plans to make the necessary software efforts 10 fully realize the capabilities of high-core count chips, including special instructions, new software tool sets, new software development tools and new software compilers."
Last year. Advanced Micro Devices Inc. announced a coherentprocessor approach to multiprocessors dubbed Torrenza and based on its proprietary HypeiTranspurt CPU bus. Intel and IBM Corp. countered with Geneseo, a set of extensions to PCI Express that manages massively parallel computers using a content-addressable memory. Startups like Ambric Inc. (Beaverton, Ore.) have announced plans for noncoherent multiprocessor research chips. Ambric's Kestrel device will pack 360 RISC processor cores.
"Intel's 80-core chip is basically a mainframe-on-a-chip-literally," said McGregor. "It's the equivalent of 80 blade processors plugged into a high-speed backplane, or 80 separate computers using a high-speed hardware interconnect." The Teraflop Research Chip's hardware does the multitasking coordination "instead of depending on software, which just could not keep up with 80 cores," he said.
Photos reveal that almost a quarter of the area of each of the 80 cores is dedicated to the mesh router, which can simultaneously coordinate communication among any adjacent cores. Also on board is a 3-D vertical...