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BERKELEY HEIGHTS, N.J. - Lucent Technologies disclosed details last week of its oft-discussed Sabre architecture and its first digital signal processor using it. As the communications industry gears for an explosion in digital wireless and wireline services, Lucent faces competition from Analog Devices Inc. and Texas Instruments Inc.
In the race to provide new architectures and price points for digital signal processing chips in wireless basestations, central-office modem pools and other network nodes, ADI will pitch a new price point for its Sharc family. Industry leader TI, meanwhile, is scrambling to get the first implmentation of its C6X Velociti architecture into the chase as well.
The Lucent chip is a member of its erstwhile Sabre family, now called the DSP16000 line. In keeping with the company's stated goal of supporting communications infrastructure needs, it is about as finely tuned for communications as a general-purpose DSP chip can be. The architecture employs dual 16-by-16-bit multiply-accumulate (MAC) units, coupled to a bank of eight 40-bit accumulators. This arrangement, working hand in hand with dualaddress calculation units, allows the chip to dispatch four operand fetches, two multiplies and two accumulates in one clock cycle from a single 32-bit instruction.
In a completely general-purpose machine, so much parallelism might be unusable to a compiler. But the DSP16210 has been closely tuned to a handful of critical functions, and can actually bring all that hardware to bear in inner loops, said Lucent strategic marketing manager Charlie Mera.
"In Viterbi algorithms, for example, there is a metric calculation where you form the squares of differences between two sets of numbers and accumulate them," he...