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SUNNYVALE, CALIF. - After five years of struggling to build acceptance for a radical DRAM architecture with a non-Jedec interface, MoSys Inc. has changed its tune. The company is set to enter two major pin-compatible markets that have huge upside potential, require no missionary work, and will still lever the advantages of the MoSys technology.
This week the company will announce a pin-compatible 256k-by32 synchronous graphics RAM ( SGRAM) with timing significantly faster than any other SGR AM in the industry. Later this year, the company is expected to announce the fruits of a long working relationship with Intel Corp.-a MoSys DRAM L2 cache for as-yet-unannounced faster grades of the Pentium-II microprocessor.
Both advances are built on the proprietary MoSys DRAM technology. In the original MoSys DRAM, the company developed an architecture of many small DRAM arrays, each with very short bit lines, and hence very fast precharge times and very small sense amps. These small arrays32 of them in the initial partwere provided with one-line SRAM caches, and connected via wide on-chip bus to a proprietary low-voltage interface.
The MDRAM, as it was called, had several advantages. They included the ability to burst data from the current row of any of the small arrays without a row-access latency, and the ability to hide the precharge time for one array behind a data burst from another array. Thus the MDRAM, though composed of DRAM cells that had finite row-access times and refresh intervals, behaved much like an SRAM.
Finding less than general acceptance for its...