Content area
Full Text
Tokyo - NEC Corp. will begin production of an ASIC process next spring featuring a 0.25-micron gate geometry that is finer than the company's best DRAM production process, EE Times learned last week. The move gives NEC a leading process position among deep-submicron ASIC vendors.
But the plans also illustrate the lengths to which suppliers will shift their capacity from free-falling DRAMs into more profitable logic products, as other DRAM suppliers in Japan, South Korea and Taiwan similarly plan to shift production capacity away from DRAM. And DRAM vendors are already worrying that the shift of so much capacity to logic will destroy margins there as it has in memories.
NEC plans to bring up 0.25-micron lines next spring at its Kyushu and Hiroshima fabrication facilities in southern Japan, and slightly later at the NEC U.K. facility at Livingston, Scotland. The three lines will initially produce memories to help debug the equipment, and will then move immediately to a mix of microprocessors, ASICs and memory products using 0.25-micron and 0.35-micron design rules.
Toshiba Corp. is among the other vendors making adjustments to its production. The company is moving to "flexible" lines that can be switched between memory and logic, said Susumu Kohyama, deputy general manager of Toshiba's semiconductor group. An early implementation of this approach will be made at the 0.25-micron, $1.3 billion logic production fab now under construction at Iwate Toshiba Electronics in northern Japan.
But NEC appears to be far ahead in the move to a flexible 0.25-micron line, which will involve many changes. Making 0.25-micron circuits will require NEC's first production-line use of excimer laser-based steppers, as well as the deposition of five interconnect layers, according to Hirokazu Hashimoto, general manager of NEC's ASIC division.
The shift also means a...