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Not only is PCI bus design a large area of design for peripherals, but the specification involves some pitfalls for newer specs, such as the Advanced Configuration and Power Interface (ACPI).
The PCI Power Management specification introduced a signal called PME#, along with configuration space registers to express a PCI device's power management capabilities and a status and enable register for PME#. Arming a PCI device for wakeup sets the PME enable bit. When the device asserts PME# to wake itself, PME enable is activated.
Many PCI device designers have rerouted their internal interrupt logic to create PME#. But the design has a problem when waking up.
The machine goes through the following steps when moving from the D3 to the DO state:
The device gets an external request (via a ringing phone, network packet or the like) that it needs to fulfill.
The device asserts PME#.
If the system was in a sleeping state, the system moves to the SO state. The ACPI driver sends a message to
the PCI driver telling it that PME# has been asserted.
The PCI driver scans the PCI bus looking for the device that is asserting PME#, thus completing IRP_MN_WAIT_WAKE.