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Get2Chip, Monterey Design prep offerings for 'second generation'
SAN MATEO, CALIF. - Logic designers looking for tools that will allow them to effectively drive physical synthesis will have a bevy of new silicon virtual-prototyping (SVP) products to check out next week when the Design Automation Conference (DAC) opens in Las Vegas.
Get2Chip.com Inc. and Monterey Design Systems Inc. have added their offerings to the growing list of vendors that will be showing what Gary Smith, chief EDA analyst at Gartner Dataquest, terms "second-generation silicon virtualprototyping tools."
"Twoyears ago we sawa trickle of companies offering IC implementation tools," said Smith. "These tools were targeted toward physical-design groups and were used at the RT [registertransfer] and gate levels. This second-generation SVP targets designers. Theywill actually help designers design better logic, whichwill in turn produce better results in IC implementation. They not only have the estimation capability but also the topdown constraint and designteam collaboration capabilities."
Other new second-generation SVP offerings announced recently come from InTime Software Inc. (see May 28, page 66), Icinergy Software (see May 7, page 61) and even Interra spin-off Atrenta, which has upped the status of its Spyglass RTL rule checker by adding a database that allows users to access several vendors' tools from one environment.
According to Smith, all these news tools help designers create chip prototypes starting at either the system or RT level. But each has varying degrees of functionality and ties to actual silicon. Icinergy and Atrenta are closely related to RT-level-and-above rule checkers, while tools from InTime, Get2Chip and Monterey have floor-plan technologies and links to varying degrees of physical information, in addition to the ability to accept RTL or...