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SAN MATEO, CALIF. - Synplicity Inc. is leveraging technology from the FPGA synthesis sector to take a run at Synopsys Inc. in the ASIC synthesis market. The Sunnyvale, Calif., company this week will release Synplify ASIC, a tool targeting mainstream ASIC designers who need to quickly ramp up synthesis and get chips out the door.
Of all the tool areas in EDA, ASIC synthesis has proven by far the hardest for companies to break into, given that Synopsys has virtually owned the market since introducing its Design Compiler (DC) more than a decade ago. But Synopsys and its competitors are moving past mainstream ASICs into bleedingedge technology known as physical synthesis, which combines synthesis and physical-implementation tools.
Synplicity thinks that migration gives it a chance to slip in the back door and cater to mainstream ASIC designers. The newly publicly traded company is also working closely with Monterey Design Systems to link the pair's respective tool suites.
Unlike other Synopsys challengers such as Ambit/Cadence, Get2Chip and newcomer Incentia, Synplicity is not looking to displace Synopsys in highend design starts. Instead, it is marketing "ease of use" -the hallmark of Synplicity's FPGA synthesis tools-as its main selling point.
"The ASIC synthesis user who has spent years creating scripts to get a synthesis tool to work the way it should is not our target customer," said Ken McElvain, chief technology officer and co-founder of Synplicity. "We are after designers who want to be able to tell the tool what they want in their design, and the tool does all the work."
"Synplicity is walking into a vacuum," said Gary Smith, the chief EDA analyst at Dataquest, who in the past has been largely skeptical of new entrants in ASIC synthesis. "All the effort today is going into targeting the problems of the power...