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If you purchase a server in the next few months featuring Intel’s Sapphire Rapids generation of Xeon Scalable processor or AMD’s Genoa generation of Epyc processors, they will come with a notable new function called Compute Express Link (CXL)—an open interconnect standard you may find useful, especially in future iterations.
CXL is supported by pretty much every hardware vendor and built on top of PCI Express for coherent memory access between a CPU and a device, such as a hardware accelerator, or a CPU and memory.
PCIe is meant for point-to-point communications such as SSD to memory, but CXL will eventually support one-to-many communication by transmitting over coherent protocols. So far, CXL is capable of simple point-to-point communication only.
CXL is currently in its 1.1 iteration, and 2.0 and 3.0 specs have been announced. Because CXL is joined at the hip with PCIe, new versions of CXL are dependent on new versions of PCIe. There is about a two-year gap in between releases of PCIe and then even longer gap between release of...