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Abstract
One of the most important tasks in the field of electronic design automation (EDA) is the functional reverse engineering (RE) of flattened Field Programmable Gate Array (FPGA) Look-Up Table (LUT) netlists to their Register Transfer Level (RTL) representation. Legacy designs can be difficult to comprehend since they often lack adequate documentation or the original design files. By converting the netlists to RTL representation, engineers can gain a better understanding of the design's functionality and make improvements or modifications easily.
Traditional netlist reverse engineering techniques can be time-consuming and error-prone as they manually examine the netlist and determine the underlying RTL structure. However, recent developments in machine learning, notably in the area of graph neural networks (GNNs), have demonstrated significant progress in addressing EDA issues.
In this thesis, we presented a tool RELUT-GNN, that extracts high-level functionality from FPGA netlists using GNNs. To achieve this, a graph representation of the netlist structure is created, with the FPGA leaf cells serving as the nodes and the connected nets serving as the edges. GNNs can efficiently capture the connections and interdependence between the various design aspects by considering the netlist as a undirected graph.
To train the GNN, a comprehensive custom dataset is constructed, which contains various data path elements commonly found in FPGA designs, such as Operators, Shifters, Counters, and Finite State Machines (FSMs). The dataset also includes combinations of these elements with varying bit widths, allowing the model to learn the diverse patterns and behaviors of different design components. During training, the GNN learns to aggregate the features of each node along with information from its neighboring nodes. This enables the model to capture the structural characteristics of the netlist and extract the high-level functionality of the sub-circuits within it.
To evaluate the performance of the proposed approach, the model is tested on real-world designs obtained from Opencores and ITC99, which provide a diverse set of benchmarks. The classification accuracy is used as the evaluation metric. Our model achieved a combined accuracy of 97.12% which indicates that the model can accurately extract the high-level functionality of FPGA netlists and represented them in their RTL counterparts.
